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PDF LTC1773 Data sheet ( Hoja de datos )
| Número de pieza | LTC1773 | |
| Descripción | No RSENSE Low EMI / Synchronous DC/DC Controller with Output Tracking | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LTC1773 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
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LTC1773
Synchronous Step-Down
DC/DC Controller
FEATURES
DESCRIPTIO
■ High Efficiency: Up to 95%
The LTC®1773 is a current mode synchronous buck regu-
■ Constant Frequency 550kHz Operation
lator controller that drives external complementary power
■ VIN from 2.65V to 8.5V
MOSFETs using a fixed frequency architecture. The oper-
■ VOUT from 0.8V to VIN
ating supply range is from 2.65V to 8.5V, making it
■ OPTI-LOOP® Compensation Minimizes COUT
■ Synchronizable up to 750kHz
m■ Selectable Burst Mode Operation
o■ Low Quiescent Current: 80µA
■ Low Dropout Operation: 100% Duty Cycle
.c■ Secondary Winding Regulation
■ Soft-Start
U■ Current Mode Operation for Excellent Line and
Load Transient Response
t4■ Low Shutdown IQ = 10µA
■ ±1.5% Reference Accuracy
e■ Precision 2.5V Undervoltage Lockout
e■ Available in 10-Lead MSOP
APPLICATIOUS Sh■ Cellular Telephones
ta■ RF PA Supplies
■ Portable Instruments
a■ Wireless MODEMS
■ Distributed Power Systems
.D■ Notebook and Palm Top Computers, PDAs
■ Single and Dual Cell Lithium-Ion Powered Devices
suitable for 1- or 2-cell lithium-ion battery powered appli-
cations. Burst Mode® operation provides high efficiency at
low load currents. 100% duty cycle provides low dropout
operation which extends operating time in battery-oper-
ated systems.
The operating frequency is internally set at 550kHz, allow-
ing the use of small surface mount inductors. For switch-
ing-noise sensitive applications, it can be synchronized up
to 750kHz. Peak current limit is user programmable with
an external high side sense resistor. A SYNC/FCB control
pin guarantees regulation of secondary windings regard-
less of load on the main output by forcing continuous
operation. Burst Mode operation is inhibited during syn-
chronization or when the SYNC/FCB pin is pulled low to
reduce noise and RF interference. Soft-start is provided by
an external capacitor.
Synchronous rectification increases efficiency and elimi-
nates the need for a Schottky diode, saving components
and board space. The LTC1773 comes in a 10-lead MSOP
package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
OPTI-LOOP and Burst Mode are registered trademarks of Linear Technology Corporation.
Protected by U.S. Patents, including 5481178, 6580258, 6304066, 6127815.
TYPICAL APPLICwATIwO VIN
w 2.65V TO 8.5V
High Efficiency
SYNC/FCB VIN
RUN/SS SENSE–
0.1µF
ITH TG
47pF
30k
LTC1773
SW
RSENSE
0.025Ω
L1
3µH
+
CIN
68µF
VOUT
2.5V
100
95 VIN = 3.3V
90 VIN = 5V
85 VIN = 8V
80
75
220pF
VFB GND BG
80.6k
Si9801DY
169k
+ COUT
180µF
1773 F01
70
65
60
L = SUMIDA CDRH6D28-3R0
55
1 10 100 1000 5000
OUTPUT CURRENT (mA)
Figure 1. Step-Down Converter
1773 F1b
1773fa
1
1 page  
LTC1773
PIN FUNCTIONS
ITH (Pin 1): Error Amplifier Compensation Point. The
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is 0V to 1.2V.
Under high duty cycle and nearing current limit, ITH can
swing up to 2.4V.
RUN/SS (Pin 2): Combination of Soft-Start and Run
Control Inputs. A capacitor to ground at this pin sets the
ramp time to full current output. The time is approximately
0.8s/µF. Forcing this pin below 0.4V shuts down all the
circuitry.
SYNC/FCB (Pin 3): Multifunction Pin. This pin performs
three functions: 1) secondary winding feedback input, 2)
external clock synchronization and 3) Burst Mode opera-
tion or forced continuous mode select. For secondary
winding applications, connect to a resistive divider from
the secondary output. To synchronize with an external
clock, apply a TTL/CMOS compatible clock with a fre-
quency between 585kHz and 750kHz. To select Burst
Mode operation, tie SYNC/FCB to VIN. Grounding this pin
forces continuous operation.
VFB (Pin 4): Feedback Pin. Receives the feedback voltage
from an external resistive divider across the output. Do not
use more than 0.01µF of feedforward capacitance from FB
to the output.
GND (Pin 5): Ground Pin.
BG (Pin 6): Bottom Gate Driver of External N-Channel
Power MOSFET. This pin swings from 0V to VIN.
TG (Pin 7): Top Gate Driver of External P-Channel Power
MOSFET. This pin swings from 0V to VIN.
VIN (Pin 8) : Main Supply Pin. Must be closely decoupled
to GND (pin 5).
SENSE–(Pin 9): The Negative Input to the Current Com-
parator. A sense resistor between this pin and VIN sets the
peak current in the top switch. Connect this pin to the
source of the external P-Channel power MOSFET.
SW (Pin 10): Switch Node Connection to Inductor. This
pin connects to the drains of the external main and
synchronous power MOSFET switches.
W
FUNCTIONAL DIAGRA
0.4µA
SYNC/FCB 3
BURST
DEFEAT
X
Y
OSC
Y = “0” ONLY WHEN X IS A CONSTANT “1”
SLOPE
COMP
8 VIN
0.4V
9 SENSE–
VFB 4
0.6V –
SYNC
DEFEAT
+
0.8V REF
UVLO
TRIP = 2.5V
SHUTDOWN
0.8V
FREQ
SHIFT
+
EA
1.5µA
–
2
RUN/SS
RURNU/SNO/ FT
SOFSTT-ASRTATRT
0.86V
–
OVDET
+
0.22V
ITH
1
0.8V –
FCB
+
Figure 2.
EN
–
50mV
SLEEP
+
BURST
COMP
–+
ICOMP
SQ
RQ
SWITCHING
LOGIC
AND
BLANKING
CIRCUIT
ANTI
SHOOT-THRU
IRCMP
7 TG
6 BG
10 SW
5 GND
1773 FD
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5
5 Page 
LTC1773
APPLICATIONS INFORMATION
drawn from the auxiliary windings without regard to the
primary output load.
The secondary output voltage is set by the turns ratio of the
transformer in conjunction with a pair of external resistors
returned to the SYNC/FCB pin as shown in Figure 5. The
secondary regulated voltage, VSEC, in Figure 5 is given by:
VSEC
≅
(N + 1)VOUT
−
VDIODE
>
0.8V⎛⎝⎜1+
R4
R3
⎞⎠⎟
where N is the turns ratio of the transformer and VOUT is
the main output voltage sensed by VFB.
LTC1773
R4 TG
SYNC/FCB
R3 SW
BG
VIN
+ VSEC
L1 1µF
1:N
VOUT
+
COUT
1773 F05
Figure 5. Secondary Output Loop Connection
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1773 circuits: VIN quiescent current, external
power MOSFET gate charge current, I2R losses, and
topside MOSFET transition losses.
1. The VIN quiescent current is due to the DC bias current
as given in the electrical characteristics, it excludes
MOSFET driver and control currents. VIN current results
in a small loss which increases with VIN.
2. The external MOSFET gate charge current results from
switching the gate capacitance of the external power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge dQ moves
from VIN to ground. The resulting dQ/dt is the current
out of VIN; it is typically larger than the DC bias current.
In continuous mode, IGATECHG = f(QT + QB) where QT
and QB are the gate charges of the external main and
synchronous switches. Both the DC bias and gate
charge losses are proportional to VIN and thus their
effects will be more pronounced at higher supply volt-
ages.
3. I2R losses are calculated from the resistances of the
external RSENSE, the external power MOSFETs (RSW)
and the external inductor (RL). In continuous mode, the
average output current flowing through inductor L is
“chopped” between the main switch and the synchro-
nous switch. Thus, the series resistance looking into
the SW pin from L is a function of both top and bottom
MOSFET RDS(ON) and the duty cycle (DC), as follows:
RSW = (RDS(ON)TOP +RSENSE) • DC + RDS(ON)BOT • (1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can
be obtained from the MOSFET manufactures’s
datasheets. Thus, to obtain I2R losses, simply add RSW
and RL together and multiply their sum by the square of
the average output current.
4. Transition losses apply to the topside MOSFET and
increase when operating at high input voltages and
higher operating frequencies. Transition losses can be
estimated from:
Transition Loss = 2(VIN)2IO(MAX)CRSS(f)
Other losses including CIN and COUT ESR dissipative
losses, and inductor core losses, generally account for
less than 2% total additional loss.
1773fa
11
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| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet LTC1773.PDF ] | |
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