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PDF LT1641 Data sheet ( Hoja de datos )

Número de pieza LT1641
Descripción Positive High Voltage Hot Swap Controller
Fabricantes Linear Technology 
Logotipo Linear Technology Logotipo



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FEATURES
s Allows Safe Board Insertion and Removal from a
Live Backplane
s Controls Supply Voltage from 9V to 80V
s Programmable Analog Foldback Current Limiting
s High Side Drive for an External N-Channel
s Automatic Retry or Latched Operation Mode
s User Programmable Supply Voltage Power-Up Rate
s Undervoltage Lockout
s Overvoltage Protection
U
APPLICATIO S
s Hot Board Insertion
s Electronic Circuit Breaker
s Industrial High Side Switch/Circuit Breaker
s 24V/48V Industrial/Alarm Systems
Final Electrical Specifications
LT1641
Positive High Voltage
Hot Swap Controller
August 1999
DESCRIPTIO
The LT®1641 is an 8-pin Hot SwapTM controller that allows
a board to be safely inserted and removed from a live
backplane. Using an external N-channel pass transistor,
the board supply voltage can be ramped up at a program-
mable rate. A high side switch driver controls an N-channel
gate for supply voltages ranging from 9V to 80V.
The chip features a programmable analog foldback cur-
rent limit circuit. If the chip remains in current limit for
more than a programmable time, the N-channel pass
transistor latches off and is optionally set to automatically
restart after a time-out delay.
The PWRGD output indicates when the output voltage,
sensed by the FB pin, is within tolerance. The ON pin
provides programmable undervoltage lockout.
The LT1641 is available in the 8-lead SO package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Hot Swap is a trademark of Linear Technology Corporation.
TYPICAL APPLICATIO
24V Input Voltage Application
VIN
24V
R1
49.9k
1%
RS
0.01
Q1
IRF530
D1
R5 CMPZ
105248B
5%
C1
R6, 10nF
1k, 5%
R3
59k
1%
VOUT
CL
8
VCC
1
ON
7
SENSE
6
GATE
LT1641
R2
3.4k
1%
2
FB
3
PWRGD
R7
24k
5%
R4
3.57k
1%
PWRGD
TIMER
GND
54
C2
0.68µF
GND
1641 TA01
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LT1641 pdf
TEST CIRCUIT
LT1641
ON VCC
FB SENSE
V+
5V
5k
PWRGD
GATE
GND
TIMER
1641 F01
+– 24V
10nF
Figure 1
TI I G DIAGRA S
ON
GATE
1.313V
1.233V
tPLHON
5V
Figure 2. ON to GATE Timing
tPHLON
1V
1641 F02
FB
PWRGD
1.313V
1.233V
tPLHFB
1V
Figure 3. FB to PWRGD Timing
tPHLFB
1V
1641 F03
VCC – SENSE
GATE
47mV
tPHLSENSE
VCC
Figure 4. SENSE to GATE Timing
1641 F04
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LT1641 arduino
LT1641
APPLICATIO S I FOR ATIO
GATE Pin Voltage
A curve of gate drive vs VCC is shown in Figure 15. The
GATE pin is clamped to a maximum voltage of 18V above
the input voltage. At minimum input supply voltage of 9V,
the minimum gate drive voltage is 4.5V. When the input
supply voltage is higher than 20V, the gate drive voltage is
at least 10V and a regular N-FET can be used. In applica-
tions ranges 9V to 24V range, a logic level N-FET must be
used with a proper protection Zener diode between its gate
and source (as D1 shown is Figure 5).
Layout Considerations
To achieve accurate current sensing, a Kelvin connection
is recommended. The minimum trace width for 1oz cop-
per foil is 0.02" per amp to make sure the trace stays at a
reasonable temperature. 0.03" per amp or wider is recom-
mended. Note that 1oz copper exhibits a sheet resistance
of about 530µΩ/ . Small resistances add up quickly in
high current applications. To make the system immune to
noise, the resistor divider to the ON pin needs to be close
to the chip and keep traces to VCC and GND short. A 0.1µF
capacitor from the ON pin to GND also helps reject induced
noise. Figure 16 shows a layout that addresses these
issues.
18
16
14
12
10
8
6
4
2
0
8
13 18
VCC (V)
23
1641 F15
Figure 15. Gate Drive vs Supply Voltage
ILOAD
R1
LT1641
SENSE
RESISTOR, RS
R2
ILOAD
1541 F16
Figure 16. Recommended Layout for R1, R2 and RS
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