PDF AM486 Data sheet ( Hoja de datos )

Número de pieza	AM486
Descripción	Enhanced Microprocessor Family
Fabricantes	AMD
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PRELIMINARY Enhanced Am486® Microprocessor Family Advanced Micro Devices DISTINCTIVE CHARACTERISTICS n High-Performance Design — Improved cache structure supports industry- standard write-back cache — Frequent instructions execute in one clock — 80-million bytes/second burst bus at 25 MHz — 105.6-million bytes/second burst bus at 33 MHz — 128-million bytes/second burst bus at 40 MHz — Flexible write-through and write-back address control — 0.5-micron CMOS process technology — Dynamic bus sizing for 8-, 16-, and 32-bit buses — Supports “soft reset” capability n High On-Chip Integration — 8-Kbyte unified code and data cache — Floating-point unit — Paged, virtual memory management n Enhanced System and Power Management — Stop clock control for reduced power consumption — Industry-standard 2-pin System Management In- terrupt (SMI) for power management independent of processor operating mode and operating system — Static design with Auto Halt power-down support — Wide range of chipsets supporting SMM avail- able to allow product differentiation n Complete 32-Bit Architecture — Address and data buses — All registers — 8-, 16-, and 32-bit data types n Standard Features — 3-V core with 5-V tolerant I/O — Available in DX2 and DX4 versions — Binary compatible with all Am486® DX and Am486DX2 microprocessors — Wide range of chipsets and support available through the AMD® FusionPCSM Program n 168-pin PGA package or 208-pin SQFP package n IEEE 1149.1 JTAG Boundary-Scan Compatibility n Supports Environmental Protection Agency's “Energy Star” program — 3-V operation reduces power consumption up to 40% — Energy management capability provides excel- lent base for energy-efficient design — Works with a variety of energy efficient, power managed devices GENERAL DESCRIPTION Table 1. Clocking Options The Enhanced Am486 microprocessor family is an ad- dition to the Am486 microprocessor family of products. CPU Type Operating Frequency Bus Speed Available Package The new family enhances system performance by incor- mporating a write-back cache implementation, flexible oclock control, and enhanced SMM. Table 1 shows avail- .cable processors in the Enhanced Am486 microproces- usor family. t4The Enhanced Am486 microprocessor family cache al- elows write-back configuration through software and ecacheable access control. On-chip cache lines are con- tashfigurable as either write-through or write-back. DX2 DX4 66 MHz 80 MHz 75 MHz 100 MHz 120 MHz 33 MHz 40 MHz 25 MHz 33 MHz 40 MHz 168-pin PGA 168-pin PGA or 208-pin SQFP 168-pin PGA The Enhanced CPU clock control feature permits the CPU clock to be stopped under controlled conditions, allowing reduced power consumption during system in- activity. The SMM function is implemented with an indus- try standard two-pin interface. w.daThis document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed ww product without notice. Publication#19225 Rev: C Amendment/0 Issue Date: March 1996 1 page PRELIMINARY AMD 4.8.9 BOFF During Write-Back ..................................................................................................... 32 4.8.10 Snooping Characteristics During a Cache Line Fill ........................................................... 32 4.8.11 Snooping Characteristics During a Copy-Back ................................................................. 32 4.9 Cache Invalidation and Flushing in Write-Back Mode .................................................................. 33 4.9.1 Cache Invalidation through Software .................................................................................. 33 4.9.2 Cache Invalidation through Hardware ................................................................................. 33 4.9.3 Snooping During Cache Flushing ........................................................................................ 34 4.10 Burst Write .................................................................................................................................. 34 4.10.1 Locked Accesses .............................................................................................................. 35 4.10.2 Serialization ....................................................................................................................... 35 4.10.3 PLOCK Operation in Write-Through Mode ........................................................................ 36 5 Clock Control ...................................................................................................................................... 36 5.1 Clock Generation .......................................................................................................................... 36 5.2 Stop Clock ..................................................................................................................................... 36 5.2.1 External Interrupts in Order of Priority ................................................................................. 36 5.3 Stop Grant Bus Cycle ................................................................................................................... 36 5.4 Pin State during Stop Grant .......................................................................................................... 37 5.5 Clock Control State Diagram ........................................................................................................ 37 5.5.1 Normal State ........................................................................................................................ 37 5.5.2 Stop Grant State .................................................................................................................. 37 5.5.3 Stop Clock State .................................................................................................................. 39 5.5.4 Auto Halt Power Down State ............................................................................................... 39 5.5.5 Stop Clock Snoop State (Cache Invalidations) .................................................................... 39 5.5.6 Cache Flush State ............................................................................................................... 39 6 SRESET Function ............................................................................................................................... 39 7 System Management Mode ................................................................................................................ 39 7.1 Overview ....................................................................................................................................... 39 7.2 Terminology .................................................................................................................................. 40 7.3 System Management Interrupt Processing ................................................................................... 40 7.3.1 System Management Interrupt Processing ......................................................................... 41 7.3.2 SMI Active (SMIACT) .......................................................................................................... 41 7.3.3 SMRAM ............................................................................................................................... 42 7.3.4 SMRAM State Save Map .................................................................................................... 43 7.4 Entering System Management Mode ............................................................................................ 44 7.5 Exiting System Management Mode .............................................................................................. 44 7.6 Processor Environment ................................................................................................................. 44 7.7 Executing System Management Mode Handler ............................................................................ 45 7.7.1 Exceptions and Interrupts with System Management Mode ............................................... 46 7.7.2 SMM Revisions Identifier ..................................................................................................... 46 7.7.3 Auto HALT Restart .............................................................................................................. 47 7.7.4 I/O Trap Restart ................................................................................................................... 47 7.7.5 I/O Trap Word ...................................................................................................................... 47 7.7.6 SMM Base Relocation ......................................................................................................... 48 7.8 SMM System Design Considerations ........................................................................................... 48 7.8.1 SMRAM Interface ................................................................................................................ 48 7.8.2 Cache Flushes .................................................................................................................... 49 7.8.3 A20M Pin ............................................................................................................................. 49 7.8.4 CPU Reset during SMM ...................................................................................................... 52 7.8.5 SMM and Second Level Write Buffers ................................................................................ 52 7.8.6 Nested SMI and I/O Restart ................................................................................................ 52 7.9 SMM Software Considerations ..................................................................................................... 52 7.9.1 SMM Code Considerations ................................................................................................. 52 7.9.2 Exception Handling ............................................................................................................. 52 7.9.3 Halt during SMM .................................................................................................................. 53 7.9.4 Relocating SMRAM to an Address above 1 Mbyte ............................................................. 53 Enhanced Am486 Microprocessor 5 5 Page PRELIMINARY AMD 1.4 208-Pin SQFP Designations (Functional Grouping) Address Data Control Test INC Vcc Vss Pin Name Pin Pin Name Pin No. No. Pin Pin Pin Name No. Name A2 202 D0 144 A20M 47 TCK A3 197 D1 143 ADS 203 TDI A4 196 D2 142 AHOLD 17 TDO A5 195 D3 141 BE0 31 TMS A6 193 D4 140 BE1 32 A7 192 D5 130 BE2 33 A8 190 D6 129 BE3 34 A9 187 D7 126 BLAST 204 A10 186 D8 124 BOFF 6 A11 182 D9 123 BRDY 5 A12 180 D10 119 BREQ 30 A13 178 D11 118 BS8 8 A14 177 D12 117 BS16 7 A15 174 D13 116 CACHE 70 A16 173 D14 113 CLK 24 A17 171 D15 112 CLKMUL 11 A18 166 D16 108 D/C 39 A19 165 D17 103 DP0 145 A20 164 D18 101 DP1 125 A21 161 D19 100 DP2 109 A22 160 D20 99 DP3 90 A23 159 D21 93 EADS 46 A24 158 D22 92 FERR 66 A25 154 D23 91 FLUSH 49 A26 153 D24 87 HITM 63 A27 152 D25 85 HLDA 26 A28 151 D26 84 HOLD 16 A29 149 D27 83 IGNNE 72 A30 148 D28 79 INTR 50 A31 147 D29 78 INV 71 D30 75 KEN 13 D31 74 LOCK 207 M/IO 37 NMI 51 PCD 41 PCHK 4 PLOCK 206 PWT 40 RDY 12 RESET 48 SMI 65 SRESET 58 STPCLK 73 SMIACT 59 UP 194 WB/WT 64 W/R 27 Pin Pin Pin Pin No. No. No. No. 18 3 2 1 168 67 9 10 68 96 14 15 167 127 19 21 20 28 22 36 23 43 25 52 29 53 35 55 38 57 42 61 44 76 45 81 54 88 56 94 60 97 62 104 69 105 77 107 80 110 82 115 86 120 89 122 95 132 98 135 102 138 106 146 111 156 114 157 121 170 128 175 131 181 133 184 134 189 136 199 137 201 139 208 150 155 162 163 169 172 176 179 183 185 188 191 198 200 205 Note: INC = Internal No Connect Enhanced Am486 Microprocessor 11 11 Page

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