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PDF BS616LV4017 Data sheet ( Hoja de datos )
| Número de pieza | BS616LV4017 | |
| Descripción | Very Low Power/Voltage CMOS SRAM 256K X 16 bit | |
| Fabricantes | BSI | |
| Logotipo |  |
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BSI Very Low Power/Voltage CMOS SRAM
256K X 16 bit
BS616LV4017
FEATURES
• Wide Vcc operation voltage : 2.4~5.5V
• Very low power consumption :
Vcc = 3.0V C-grade: 26mA (@55ns) operating current
I-grade: 27mA (@55ns) operating current
C-grade: 21mA (@70ns) operating current
I-grade: 22mA (@70ns) operating current
0.45uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade: 63mA (@55ns) operating current
I-grade: 65mA (@55ns) operating current
C-grade: 53mA (@70ns) operating current
I-grade: 55mA (@70ns) operating current
2.0uA (Typ.) CMOS standby current
• High speed access time :
-55 55ns
-70 70ns
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
DESCRIPTION
The BS616LV4017 is a high performance, very low power CMOS Static
Random Access Memory organized as 262,144 words by 16 bits and
operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.45uA at 3.0V/25oC and maximum access time of 55ns at 3.0V/85oC.
Easy memory expansion is provided by an active LOW chip enable (CE)
,active LOW output enable(OE) and three-state output drivers.
The BS616LV4017 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV4017 is available in DICE form, JEDEC standard 44-pin
TSOP Type II package and 48-ball BGA package.
PRODUCT FAMILY
PRODUCT FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
BS616LV4017DC
BS616LV4017EC
BS616LV4017AC
BS616LV4017DI
BS616LV4017EI
BS616LV4017AI
+0 O C to +70O C
-40 OC to +85 OC
PIN CONFIGURATIONS
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VCC
GND
DQ4
DQ5
DQ6
DQ7
WE
A17
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
BS616LV4017EC
BS616LV4017EI
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
A12
2.4V ~ 5.5V
2.4V ~ 5.5V
SPEED
( ns )
55ns :3.0~5.5V
70ns :2.7~5.5V
POWER DISSIPATION
STANDBY
Operating
( I CCSB1 , Max )
( I CC , Max )
Vcc= 3.0V Vcc= 5.0V
Vcc =3.0V
70ns
Vcc =5.0V
70ns
55 /70
5uA 30uA 21mA 53mA
55 /70
10uA 60uA 22mA 55mA
BLOCK DIAGRAM
PKG TYPE
DICE
TSOP2-44
BGA-48-0608
DICE
TSOP2-44
BGA-48-0608
A4
A3
A2
A1
A0
A17
A16
A15
A14
A13
A12
DQ0
.
.
.
.
DQ15
Address
Input
Buffer
22
Row
2048
Decoder
Data
16
Input
16
. Buffer
.
. 16
.
Data
Output
16
Buffer
Memory Array
2048 x 2048
2048
Column I/O
Write Driver
Sense Amp
128
Column Decoder
CE
WE
OE
UB
LB
Vcc
Gnd
Control
14
Address Input Buffer
A11 A10 A9 A8 A7 A6 A5
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
R0201-BS616LV4017
1
Revision 2.1
Jan. 2004
1 page  
BSI
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Vcc / 0V
Input Rise and Fall Times
1V/ns
Input and Output
Timing Reference Level
Output Load
0.5Vcc
CL = 30pF+1TTL
CL = 100pF+1TTL
BS616LV4017
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
DON , T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
READ CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
AVQV
t
ELQV
t
BA
t
GLQV
t
E1LQX
t
BE
t
GLQX
t
EHQZ
t
BDO
t
GHQZ
t
AXOX
PARAMETER
NAME
t
RC
t
AA
t
ACS
t (1)
BA
t
OE
t
CLZ
t
BE
t
OLZ
t
CHZ
t
BDO
t
OHZ
t
OH
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
Data Hold from Address Change
(LB,UB)
(LB,UB)
(LB,UB)
CYCLE TIME : 70ns
(Vcc = 2.7~5.5V)
MIN. TYP. MAX.
70 -- --
-- -- 70
-- -- 70
-- -- 35
-- -- 35
10 --
--
5 -- --
5 -- --
-- -- 35
-- -- 35
-- -- 30
10 --
--
CYCLE TIME : 55ns
(Vcc = 3.0~5.5V)
MIN. TYP. MAX.
55 --
--
-- -- 55
-- -- 55
-- -- 30
-- -- 30
10 --
--
5 -- --
5 -- --
-- -- 30
-- -- 30
-- -- 25
10 --
--
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE :
1. tBA is 35ns/30ns (@speed=70ns/55ns) with address toggle. ; tBA is 70ns/55ns (@speed=70ns/55ns) without address toggle.
R0201-BS616LV4017
5
Revision 2.1
Jan. 2004
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet BS616LV4017.PDF ] | |
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