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Número de pieza MSM6698
Descripción 80-DOT COMMON DRIVER
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No Preview Available ! MSM6698 Hoja de datos, Descripción, Manual

E2B0030-27-Y2
¡¡SemicondSucetormiconductor
MSM6698
80-DOT COMMON DRIVER
This version: NMovS.M19696798
Previous version: Mar. 1996
GENERAL DESCRIPTION
The MSM6698 is a dot matrix LCD common driver. Fabricated in CMOS technology, the device
consists of an 80-bit bi-directional shift register, 80-bit level shifter, and 80-bit 4-level driver.
The MSM6698 is equipped with 80 LCD output pins. By connecting more than two MSM6698s
in series, this LSI is applicable to a wide LCD panel.
FEATURES
• Logic supply voltage
: 2.7 to 5.5 V
• LCD drive voltage
: 18 to 28 V
• Applicable LCD duty
: 1/64 to 1/240
• Interface with MSM6599B (80-dot segment driver)
• Package:
100-pin plastic QFP (QFP100-P-1420-0.65-K) (Product name: MSM6698GS-K)
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MSM6698 pdf
¡ Semiconductor
MSM6698
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter
Symbol
Condition
(VDD = 2.7 to 5.5V, Ta = –20 to +75°C)
Min. Typ. Max. Unit
"H" Input Voltage
"L" Input Voltage
"H" Input Current
"L" Input Current
"H" Output Voltage
"L" Output Voltage
ON Resistance
Logic Supply Current
LCD Supply Current
Input Capacitance
VIH *1
0.8VDD
VIL *1
VSS
IIH *1 VI = VDD, VDD = 5.5V
IIL *1 VI = 0V, VDD = 5.5V
VOH *2 IO = –0.2mA, VDD = 2.7V VDD – 0.4
VOL *2 IO = 0.2mA, VDD = 2.7V
RON
*4
VDD – VEE = 25V
| VN – VO | =0.25V
*3
ISS fCP = 28kHz, VDD = 3.0V
IEE VDD – VEE = 25V, No load
CI f = 1MHz
VDD
0.2VDD
1
–1
0.4
2.0
50
300
V
V
mA
mA
V
V
kW
mA
pF
*1 Applicable to CP, IO1, IO80, SHL, DF, DISP OFF.
*2 Applicable to IO1, IO80.
*3 VN = VDD to VEE, V2 = 1/16 (VDD – VEE), V5 = 15/16 (VDD – VEE), VDD = V1, VDD = 4.5V
VDD = VDDR = VDDL, V1 = V1R = V1L, V2 = V2R = V2L, V5 = V5R = V5L, VEE = VEER = VEEL
*4 Applicable to O1 to O80
Switching Characteristics
Parameter
Symbol
(VDD = 2.7 to 5.5V, Ta = –20 to +75°C, CL = 15pF)
Condition
Min. Typ. Max. Unit
"H", "L" Propagation Delay Time
Clock Frequency
CP Pulse Width
Data Setup Time
IO1 (IO80) Æ CP
Data Hold Time
CP Æ IO1 (IO80)
Rise / Fall Time of CP
tPLH, tPHL
fCP
tWCP
tSETUP
tHOLD
tr (CP), tf (CP)
——
——
63 —
100 —
100 —
——
3 ms
1 MHz
— ns
— ns
— ns
20 ns
Note1:
When display control by the DISPOFF pin is performed, CP rise and fall time must be
£ 1 ms.
tWCP
tf(CP)
tr(CP)
CP
IO1 (IO80)
IO80 (IO1)
0.8VDD
0.8VDD
tSETUP
0.2VDD
tHOLD
0.8VDD
0.2VDD
0.8VDD
0.2VDD
tPLH (tPHL)
0.8VDD
0.2VDD
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