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PDF ICM7228 Data sheet ( Hoja de datos )
| Número de pieza | ICM7228 | |
| Descripción | 8-Digit / Microprocessor- Compatible / LED Display Decoder Driver | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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®
Data Sheet
December 6, 2005
ICM7228
FN3160.8
8-Digit, Microprocessor-Compatible, LED
Display Decoder Driver
The Intersil ICM7228 display driver interfaces
microprocessors to an 8-digit, 7-segment, numeric LED
display. Included on chip are two types of 7-segment
decoder, multiplex scan circuitry, LED display segment
drivers, LED display digit drivers and an 8-byte static
memory as display RAM.
Data can be written to the ICM7228A and ICM7228B’s display
RAM in sequential 8-digit update or in single-digit update
format. Data is written to the ICM7228C display RAM in parallel
random access format. The ICM7228A and ICM7228C drive
common anode displays. The ICM7228B drives common
cathode displays. All versions can display the RAM data as
either Hexadecimal or Code B format. The ICM7228A and
ICM7228B incorporate a No Decode mode allowing each bit of
each digit's RAM word to drive individual display segments
resulting in independent control of all display segments. As a
result, bargraph and other irregular display segments and
formats can be driven directly by this chip.
The Intersil ICM7228 is an alternative to both the Maxim
ICM7218 and the Intersil ICM7218 display drivers. Notice that
the ICM7228A/B has an additional single digit access mode.
This could make the Intersil ICM7218A/B software incompatible
with ICM7228A/B operation.
Features
• Pb-Free Plus Anneal Available (RoHS Compliant)
• Improved 2nd Source to Maxim ICM7218
• Fast Write Access Time of 200ns
• Multiple Microprocessor Compatible Versions
• Hexadecimal, Code B and No Decode Modes
• Individual Segment Control with “No Decode” Feature
• Digit and Segment Drivers On-Chip
• Non-Overlapping Digits Drive
• Common Anode and Common Cathode LED Versions
• Low Power CMOS Architecture
• Single 5V Supply
Applications
• Instrumentation
• Test Equipment
• Hand Held Instruments
• Bargraph Displays
• Numeric and Non-Numeric Panel Displays
• High and Low Temperature Environments where LCD
Display Integrity is Compromised
Ordering Information
PART NUMBER
PART MARKING
DATA ENTRY
PROTOCOL
TEMP. RANGE
DISPLAY TYPE
(oC)
PACKAGE
PKG. DWG. #
ICM7228AIBI
ICM7228AIBI
Sequential
Common Anode
-40 to 85 28 Ld SOIC
M28.3
ICM7228AIBIZ (Note) 7228AIBIZ
Sequential
Common Anode
-40 to 85 28 Ld SOIC (Pb-free) M28.3
ICM7228AIPI
ICM7228AIPI
Sequential
Common Anode
-40 to 85 28 Ld PDIP
E28.6
ICM7228AIPIZ (Note) ICM7228AIPI
Sequential
Common Anode
-40 to 85 28 Ld PDIP* (Pb-free) E28.6
ICM7228BIBI
ICM7228BIBI
Sequential
Common Cathode
-40 to 85 28 Ld SOlC
M28.3
ICM7228BIBIZ (Note) ICM7228BIBIZ Sequential
Common Cathode
-40 to 85 28 Ld SOlC (Pb-free) M28.3
ICM7228BIPI
ICM7228BIPI
Sequential
Common Cathode
-40 to 85 28 Ld PDIP
E28.6
ICM7228BIPIZ (Note) ICM7228BIPIZ Sequential
Common Cathode
-40 to 85 28 Ld PDIP (Pb-free) E28.6
ICM7228CIBI
ICM7228CIBI
Random
Common Anode
-40 to 85 28 Ld SOlC
M28.3
ICM7228CIBIZ (Note) ICM7228CIBIZ Random
Common Anode
-40 to 85 28 Ld SOlC (Pb-free) M28.3
ICM7228CIPI
ICM7228CIPI
Random
Common Anode
-40 to 85 28 Ld PDIP
E28.6
ICM7228CIPIZ (Note) ICM7228CIPI
Random
Common Anode
-40 to 85 28 Ld PDIP (Pb-free) E28.6
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002-2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ICM7228
Electrical Specifications
PARAMETER
VDD = +5.0V ±10%, VSS = 0V, Unless Otherwise Specified (Continued)
TA = 25oC
TEST CONDITIONS
MIN TYP MAX
-40oC TO 85oC
MIN TYP MAX
Input Leakage Current, IIL
All Inputs Except Pin 9, ICM7228C,
VIN = VSS
--
All Inputs Except Pin 9, ICM7228C,
VIN = 5.0V
--
Display Scan Rate, fMUX
Per Digit
- 390
Inter-Digit Blanking Time, tIDB
2 10
Logical “1” Input Voltage, VINH
Three Level Input: Pin 9
ICM7228C, Hexadecimal VDD = 5V
4.2 -
Floating Input, VINF
Three Level Input: Pin 9
ICM7228C, Code B, VDD = 5V
2.0 -
Logical “0” Input Voltage, VINL
Three Level Input: Pin 9
ICM7228C, Shutdown, VDD = 5V
--
Three Level Input Impedance, ZIN VCC = 5V, Pin 9 of ICM7228C
50 -
Logical “1” Input Voltage, VIH
All Inputs Except, Pin 9 of ICM7228C, 2.0 -
VDD = 5V
Logical “0” Input Voltage, VIL
All Inputs Except, Pin 9 of ICM7228C, - -
VDD = 5V
SWITCHING SPECIFICATIONS VDD = +5.0V ±10%, VSS = 0V, VIL = +0.4V, VIH = +2.4V
Write Pulsewidth (Low), tWL
200 100
Write Pulsewidth (High), tWH
850 540
Mode Hold Time, tMH
ICM7228A, ICM7228B
0 -65
Mode Setup Time, tMS
ICM7228A, ICM7228B
250 150
Data Setup Time, tDS
250 160
Data Hold Time, tDH
0 -60
Digit Address Setup Time, tAS
ICM7228C
250 110
Digit Address Hold Time, tAH
ICM7228C
0 -60
1- -
-1 -
-
- - 390
-2-
- 4.2 -
3.0 2.0
-
0.8 -
-
- 50 -
- 2.0 -
0.8 -
-
- 250 -
- 1200 -
-0-
- 250 -
- 250 -
-0-
- 250 -
-0-
1
-1
-
-
-
3.0
0.8
-
-
0.8
-
-
-
-
-
-
-
-
UNITS
µA
Hz
µs
V
V
V
kΩ
V
V
ns
ns
ns
ns
ns
ns
ns
ns
5
5 Page 
ICM7228
Sequential 8-Digit Update
The logic state of DATA COMING (lD7) is also latched
during a Control Register update. If the latched value of
DATA COMING (lD7) is high, the display becomes blanked
and a sequential 8-digit update is initiated. Display data can
now be written into RAM with 8 successive WRITE pulses,
starting with digit 1 and ending with digit 8 (See Figure 2).
After all 8 RAM locations have been written to, the display
turns on again and the new data is displayed. Additional
write pulses are ignored until a new Control Register update
is performed. All 8 digits are displayed in the format
(Hex/Code B or No Decode) specified by the control word
that preceded the 8 digit update. If a decoding scheme
(Hex/Code B) is to be used, the value of lD3 during the
control word update determines which RAM bank will be
written to.
Single Digit Update
In this mode each digit data in the display RAM can be updated
individually without changing the other display data. First, with
MODE input high, a control word is written to the Control
Register carrying the following information; DATA COMING
(lD7) low, the desired display format data on lD4 - lD6, the RAM
bank selected by lD3 (if decoding is selected) and the address
of the digit to be updated on data lines lD0 - lD2 (See Table 4).
A second write to the ICM7228A/B, this time with MODE input
low, transfers the data at the lD0 - lD7 inputs into the selected
digit’s RAM location. In single digit update mode, each
individual digit’s data can be specified independently for being
displayed in Decoded or No-Decode mode. For those digits
which decoding scheme (Hex/Code B) is selected, only one
can be effective at a time. Whenever a control word is written,
the specified decoding scheme will be applied to all those digits
which selected to be displayed in Decoded mode.
I/O OR
MEMORY
WRITE PULSE
A1-A15
DATA BUS D0-D7
DECODER
ENABLE
ADDRESS
DECODER
D0 - D7
DEVICE SELECT
AND
WRITE PULSE
A0
ID0
ID7 INTERSIL
ICM7228A/B
SEGMENTS
WRITE
DRIVE
MODE
DIGITS
DRIVE
LED DISPLAY
ADDRESS BUS A0 - A15
FIGURE 9. ICM7228A/B MICROPROCESSOR SYSTEM INTERFACING
TABLE 4. DIGITS ADDRESS, ICM7228A/B
INPUT DATA LINES
1D2 lD2
lD0 SELECTED DIGIT
000
DlGlT 1
001
DlGlT 2
010
DIGlT 3
011
DlGlT 4
100
DIGIT 5
101
DlGlT 6
110
DlGlT 7
111
DlGlT 8
System Interfacing, ICM7228C
The ICM7228C is directly compatible with the architecture of
most microprocessor systems. Its fast switching
characteristics make it possible to access them as a memory
mapped I/O device with no wait state necessary in most
microcontroller systems. All the ICM7228C inputs, excluding
HEXA/CODE B/SHUTDOWN, feature a 250ns minimum
setup and 0ns hold time with a 200ns minimum WRITE pulse.
Input logic levels are TTL and CMOS compatible. Figure 10
shows a generic method of driving the ICM7228C from a
microprocessor bus. To the microprocessor, the 8 bytes of the
Display RAM appear to be 8 separate I/O locations. Loading
the ICM7228C is quite similar to a standard memory write
cycle. The address of the digit to be updated is placed on lines
DA0 - DA2, the data to be written is placed on lines ID0 - lD3
and ID7, then a low pulse on WRITE input will transfer the
data in. See Figure 3 and Switching Characteristics Table for
write cycle timing parameters.
The ICM7228C does not have any control register, and also
does not provide the No Decode display format. Hexadecimal
or Code B character selection and shutdown mode are directly
controlled through the three level input at Pin 9, which is
accordingly called HEXA/CODE B/SHUTDOWN. See Table 3
for input and output definitions of the ICM7228C.
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet ICM7228.PDF ] | |
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