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PDF MC74VHC04 Data sheet ( Hoja de datos )
| Número de pieza | MC74VHC04 | |
| Descripción | Hex Inverter | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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ON Semiconductort
Hex Inverter
The MC74VHC04 is an advanced high speed CMOS inverter
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7V, allowing the interface of 5V systems
to 3V systems.
• High Speed: tPD = 3.8ns (Typ) at VCC = 5V
• Low Power Dissipation: ICC = 2μA (Max) at TA = 25°C
• High Noise Immunity: VNIH = VNIL = 28% VCC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2V to 5.5V Operating Range
• Low Noise: VOLP = 0.8V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 36 FETs or 9 Equivalent Gates
w These devices are available in Pb−free package(s). Specifications herein
apply to both standard and Pb−free devices. Please see our website at
www.onsemi.com for specific Pb−free orderable part nuwwmw.DbaetarSsh,eeot4rU.com
contact your local ON Semiconductor sales office or representative.
MC74VHC04
D SUFFIX
14−LEAD SOIC PACKAGE
CASE 751A−03
DT SUFFIX
14−LEAD TSSOP PACKAGE
CASE 948G−01
M SUFFIX
14−LEAD SOIC EIAJ PACKAGE
CASE 965−01
ORDERING INFORMATION
MC74VHCXXD
MC74VHCXXDT
MC74VHCXXM
SOIC
TSSOP
SOIC EIAJ
1
A1
A2 3
5
A3
9
A4
A5 11
A6 13
2
Y1
4 Y2
6
Y3
Y=A
8
Y4
10 Y5
12 Y6
Figure 1. LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Outputs
AY
LH
HL
VCC A6 Y6 A5 Y5 A4 Y4
14 13 12 11 10 9 8
1234567
A1 Y1 A2 Y2 A3 Y3 GND
Figure 2. Pinout: 14−Lead Packages (Top View)
© Semiconductor Components Industries, LLC, 2006
March, 2006 − Rev. 4
1
Publication Order Number:
MC74VHC04/D
1 page  
OUTLINE DIMENSIONS
DT SUFFIX
TSSOP
CASE 948G−01
ISSUE O
0.15 (0.006) T U S
2X L/2 14
L
PIN 1
IDENT.
1
14X K REF
0.10 (0.004) M T U S V S
8
B
−U−
7
N 0.25 (0.010)
M
N
F
DETAIL E
0.15 (0.006) T U S
A
−V−
K
J J1 ÇÇÇÇÉÉK1ÇÇÉÉ
SECTION N−N
0.10 (0.004)
−T− SEATING
PLANE
D
C
G
H DETAIL E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
−W−
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC
0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC
0.252 BSC
M 0_ 8_ 0_ 8_
http://onsemi.com
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| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet MC74VHC04.PDF ] | |
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