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PDF LC75348 Data sheet ( Hoja de datos )
| Número de pieza | LC75348 | |
| Descripción | Single-Chip Electronic Volume and Tone Control System | |
| Fabricantes | Sanyo Electric | |
| Logotipo |  |
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Ordering number : ENN7308
CMOS IC
LC75348, 75348M
Single-Chip Electronic Volume and
Tone Control System
Overview
The LC75348 and LC75348M are electronic volume and
tone control ICs that provide volume, balance, 2-band
equalizer, input gain control, and input switching
functions while requiring a minimal number of external
components.
Functions
• Volume: 81 levels: 0 dB to –79 dB (in 1 dB steps) and
–∞.
The left and right channels are controlled independently,
allowing a balance function to be implemented.
• Bass: Peaking characteristics bass control with ±20 dB
range in 2 dB steps.
• Treble: Shelving characteristics treble control with ±10
dB range in 2 dB steps.
• Selector: One of 4 inputs can be selected for both left
and right channels.
• Input gain: Input signal amplification from 0 to +30 dB
(in 2 dB steps)
Features
• Built-in buffer amplifiers reduce the number of external
components required.
• Fabricated in a silicon gate CMOS process for minimal
switching noise from built-in switches and minimal
switching noise even when there is no input signal.
• Built-in zero cross circuits minimize switching noise
when input signals are present.
• Built-in VDD/2 reference voltage generator circuit.
• All functions are controlled from serial data. Supports
the CCB bus.
Package Dimensions
unit: mm
3196-DIP30SD
[LC75348]
27.0
30 16
1 15
0.95
(1.04)
1.78
0.48
3216-MFP30SD
30
[LC75348M]
16
SANYO: DIP30SD
1 15 0.15
15.2
0.4 1.0 (0.6)
SANYO: MFP30SD
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
13103RM (OT) No. 7308 -1/21
1 page  
LC75348, 75348M
Control System Timing and Data Format
The stipulated serial data must be input to the CL, DI, and CE pins to control the LC75348 and LC75348M. The data
structure has a total of 40 bits, of which 8 bits are address and 32 bits are data.
CE
DI B0 B1 B2 B3 A0 A1 A2 A3 D0 D1 D2 D3 D4 D5
D25 D26 D27 D28 D29 D30 D31
CL
CE
1µs 1µs 1µs
min min min
CL
1µs min
1µs min
DI
1µs ≤ TDEST
• Address code (B0 to A3)
The data has an 8-bit address code, which allows this IC to be used with the SANYO CCB serial bus.
Address code (LSB)
B0 B1 B2 B3 A0 A1 A2 A3
0 1 0 0 0 0 0 1 (82HEX)
• Control code allocation
Input switching control D0 D1 D2 D3 Operation
(L1, L2, L3, L4,
0 0 0 0 L1 (R1) ON
R1, R2, R3, R4)
1 0 0 0 L2 (R2) ON
0 1 0 0 L3 (R3) ON
1 1 0 0 L4 (R4) ON
No. 7308 -5/21
5 Page 
Continued from preceding page.
Pin No.
Pin
LC75348, 75348M
Function
• 1/2 VDD voltage generator used for the analog system
ground
28 Vref
A capacitor of about 10 µF must be connected between
Vref and AVSS (VSS) to minimize power supply ripple.
3 VSS • Ground
29 VDD • Power supply
• Time setting for the zero cross circuit no signal state time.
27 TIM If no zero cross is recognized between the time the data is
stored and the time this timer completes, the data is
acquired forcibly.
• Chip enable
2 CE Data is written to the internal latch and the analog switches
operate when this pin goes from high to low. Data transfers
are enabled when this pin is high.
1 DI • Inputs for the clock and serial data signals used to control
30 CL this IC
• Electronic volume control test pin.
4 TEST
This pin must be tied to the VSS level.
15 • Unused (no connection) pins. These pins must be either
16 NC left open or tied to VSS.
Notes
VDD
VDD
VDD
VDD
No. 7308 -11/21
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet LC75348.PDF ] | |
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