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PDF MAX3804 Data sheet ( Hoja de datos )
| Número de pieza | MAX3804 | |
| Descripción | 12.5Gbps Settable Receive Equalizer | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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19-2713; Rev 1; 11/03
EVAALVUAAILTAIOBNLEKIT
12.5Gbps Settable Receive Equalizer
General Description
The MAX3804 driver with integrated analog equalizer
compensates up to 20dB of loss at 5GHz. It is designed
to ensure PC board signal integrity up to 12.5Gbps,
where frequency-dependent skin effect and dielectric
losses typically produce unacceptable amounts of inter-
symbol interference. The MAX3804 can extend the practi-
cal chip-to-chip transmission distance for 10Gbps NRZ
serial data up to 30in (0.75m) on FR-4, and it significantly
decreases deterministic jitter. Residual jitter after equal-
ization for 10.7Gbps signals is typically 24psP-P on the
maximum path length.
The MAX3804 is ideal for 10Gbps chip-to-chip serial
interconnections on inexpensive FR-4 material. Its
3mm ✕ 3mm package affords optimal placement and
routing flexibility. It has separate VCC connections for
internal logic and current-mode logic (CML) I/O. This
allows the CML input and output to be referenced to iso-
lated supplies, providing independent DC-coupled inter-
facing to 1.8V, 2.5V, or 3.3V ICs. Eight discrete levels of
input equalization can be selected through a digital con-
trol input, enabling the equalizer to be matched to a
range of transmission line path loss. When correctly set to
match the path loss, the MAX3804 provides optimal per-
formance over a wide range of data rates and formats.
Applications
OC-192 and 10Gb Ethernet Switches and Routers
OC-192 and 10Gb Ethernet Serial Modules
High-Speed Signal Distribution
Features
o Compensates Up to 30in (0.75m) of 6-mil FR-4
Transmission Line Loss
o 115mW Operating Power
o Up to 12.5Gbps Data Rate
o Compatible with 8B10B, 64B66B, and PRBS Data
o Less than 30psP-P Residual Jitter After
Equalization
o 3-Bit Equalization Level Select Input
o 3mm x 3mm Thin QFN Package
o DC-Coupling to 1.8V, 2.5V, or 3.3V CML I/O
o -40°C to +85°C Operation
o +3.3V Core Supply Voltage
Ordering Information
PART
MAX3804ETE
TEMP RANGE
PIN-
PACKAGE
PACKAGE CODE
-40°C to +85°C 16 Thin QFN T1633F-3
(3mm x 3mm)
Pin Configuration appears at end of data sheet.
Typical Operating Circuit
+1.8V
+2.5V
+3.3V
VCC
10Gbps
SERIAL OPTICAL
MODULE SDO+
30in OF FR-4 STRIPLINE OR
MICROSTRIP TRANSMISSION LINE
VCC1 VCC VCC2
SDI+ MAX3804 SDO+
IN SDO-
+3.3V
SDI- SDO-
EQ1 EQ2 EQ3 GND
VCC
10Gbps
SERDES
SDI+
SDI-
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
12.5Gbps Settable Receive Equalizer
Pin Description
PIN
1, 4
2
3
5
6
7
8, 16
9, 12
10
11
13, 14
15
EP
NAME
FUNCTION
VCC1
CML Input Supply Voltage. Connect to +1.8V to +3.3V for DC-coupled CML. Input can also be
AC-coupled.
SDI+
Positive Serial Data Input, CML
SDI-
Negative Serial Data Input, CML
EQ1
Equalizer Boost Control Logic Input LSB, LVTTL. See Table 1.
EQ2
Equalizer Boost Control Logic Input, LVTTL. See Table 1.
EQ3
Equalizer Boost Control Logic Input MSB, LVTTL. See Table 1.
GND
Supply Ground
VCC2
CML Output Supply Voltage. Connect to +1.8V to +3.3V for DC-coupled CML. Output can also be
AC-coupled.
SDO-
Negative Serial Data Output, CML
SDO+
Positive Serial Data Output, CML
N.C.
No Connection. Leave unconnected.
VCC +3.3V Core Supply Voltage
Exposed Pad
Ground. Must be soldered to the circuit board ground for proper thermal and electrical performance
(see the Package and Layout Considerations section).
Detailed Description
General Theory of Operation
The MAX3804’s low-noise linear input stage includes
two amplifiers, one with flat-frequency response, and
one with response that compensates for the loss
characteristic of an FR-4 PC board transmission line.
A current-steering network allows the designer to
control the amount of equalization to match the path
loss for specific applications. This network consists of a
pair of variable attenuators feeding into a summing
node. Equalization is set by a 3-bit LVTTL-compatible
input (EQ3, EQ2, and EQ1). By employing fixed control
of the equalization level, the MAX3804 provides optimal
performance for a specific path loss. A high-speed
limiting amplifier follows the equalizer circuitry to shape
the output signal (see Figure 1).
CML Input and Output Buffers
The MAX3804 input and output CML buffers are termi-
nated with 50Ω to VCC1 and VCC2, respectively. The
equivalent circuit for the output is shown in Figure 2.
Separate supply voltage connections are provided for
the core (VCC), input (VCC1), and output (VCC2) circuit-
ry to control noise coupling, and to allow DC-coupling
to +1.8V, +2.5V, or +3.3V CML ICs. The CML inputs
and outputs can also be AC-coupled.
Use AC-coupling for single-ended cable applications.
The unused CML input must be connected through an
AC-coupling capacitor to a 50Ω termination.
The low-frequency cutoff of the input-stage offset-can-
cellation circuit is nominally 21kHz.
_______________________________________________________________________________________ 5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet MAX3804.PDF ] | |
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