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PDF SP8855 Data sheet ( Hoja de datos )
| Número de pieza | SP8855 | |
| Descripción | 2.8GHz Parallel Load Professional Synthesiser | |
| Fabricantes | Mitel Networks | |
| Logotipo |  |
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SP8855E
2.8GHz Parallel Load Professional Synthesiser
Advance Information
Supersedes version in January 1996 Professional Products IC Hanbook, HB2480-3.0
DS4239 - 3.0 March 1999
The SP8855E is one of a family of parallel load
synthesisers containing all the elements apart from the loop
amplifier to fabricate a PLL synthesis loop. Other devices in
the series are the SP8852E which is a fully programmable
device requiring two 16 bit words to set the RF and reference
counters, and the SP8854E which has hard wired reference
counter programming and requires a single bit word to pro-
gram the RF divider. The SP8855E replaces the existing
SP8855D.
The SP8855E is intended for applications where a fixed
synthesiser frequency is required although it can also be used
where frequency selection is set by switches. In general the
device will be programmed by connecting the programming
pins to either VCC or ground. Additional hard wired inputs can
be used to control the Fpd and Fref outputs set the control
direction of the loop and select the phase detector gain.
Another input may be used to disable the phase detector
output.
The device is available in both plastic (HP) and ceramic
(HC) J-leaded 44-lead chip carrier. Ambient temperature
ranges available are shown in the ordering information.
FEATURES
s 2.8GHz Operating Frequency (IG GRADE)
s Single 5V Supply Operation
s High Comparison Frequency 50MHz
s High Gain Phase Detector 1mA/rad
s Programmable Phase Detector Gain
s Zero "Dead Band" Phase Detector
s Wide range of RF and Reference Divide Ratios
s Programming by Hard Wired Inputs
s Low cost plastic package option
s GPS HI-REL level a screened option
ABSOLUTE MAXIMUM RATINGS
Supply voltage
-0.3V to 6V
Storage temperature
-65 °C to +150°C
Operating temperature
-55°C to +100°C
Prescaler & reference Input Voltage
2.5V p-p
Data Inputs
Junction temperature
VCC +0.3V
VEE -0.3V
+ 175°C (HC package)
+ 150°C (HP package)
PIN 1
OPTIONAL
PIN 1
REFERENCE
HC44
Pin Description
1 Input bus bit 10
2 Input bus bit 9
3 Input bus bit 8
4 Input bus bit 7
5 Input bus bit 6
6 Input bus bit 5
7 Input bus bit 4
8 Input bus bit 3
9 Input bus bit 2
10 Input bus bit 1
11 Input bus bit 0
12 0V (prescaler)
13 RF input
14 RF input
15 VCC + 5V (prescaler)
16 VEE 0V
17 Lock detect output
18 C-lock detect
19 Rset
20 Charge pump output
21 Charge pump ref.
22 Fref/Fpd enable
HP44
Pin Description
23 Control Direction
24 Fpd*
25 Fref*
26 +5V
27 Ref. osc capacitor
28 Ref in/XTAL
29 Reference bit 9
30 Reference bit 8
31 Reference bit 7
32 Reference bit 6
33 Reference bit 5
34 Reference bit 4
35 Reference bit 3
36 Reference bit 2
37 Reference bit 1
38 Reference bit 0
39 Phase Detect Enable
40 Phase Detect Gain 1
41 Phase Detect Gain 0
42 Input bus bit 13
43 Input bus bit 12
44 Input bus bit 11
*Fpd and Fref outputs are reversed using the Control Direction
input. The table above is correct when pin 23 is high.
Fig.1 Pin connections - top view
1 page  
TYPICAL OVERLOAD
+20
SP8855E
+10
+7
GUARANTEED
OPERTAING
WINDOW
-5
-10
OPERATING
AREA FOR
'IG' PARTS
ONLY
-20
-30
100MHz
TYPICAL SENSITIVITY
1GHz
2.7GHz 2.8GHz
2GHz
INPUT DRIVE REQUIREMENTS
Fig. 3 SP8855E
10GHz
+j0.5
+j1
+j0.2
0
1.1GHz
-j0.2
0.2 0.5
1
+j2
Zo = 50Ω
2.5GHz
50MHz
-j0.5
-j2
-j1
Fig. 4 R.F. input impedance
5
5 Page 
SP8855E
A minimum value for the pull down resistor is 330 Ohms. When
the Fpd and Fref outputs are disabled the output level will be at
the logic low level of about 3.5V so that the additional supply
current due to the load resistors will be present even when the
outputs are disabled.
Reference input
The reference input circuit functions as an input amplifier or
crystal oscillator. When an external reference signal is used
this is simply AC coupled to pin 28, the base of the input
emitter follower. When a low phase noise synthesiser is
required the reference signal is critical since any noise present
here will be multiplied by the loop. To obtain the lowest
possible phase noise from the SP8855E it is best to use the
highest possible reference input frequency and to divide this
down internally to obtain the required frequency at the phase
detector. The amplitude of the reference input is also
important, and a level close to the maximum will give the
lowest noise. When the use of a low reference input frequency
say 4-10MHz is essential some advantage may be gained by
using a limiting amplifier such as a CMOS gate to square up
the reference input.
In cases where a suitable reference signal is not available,
it may be more convenient to use the input buffer as a crystal
oscillator in this case the emitter follower input transistor is
connected as a Colpitts oscillator with the crystal connected
from the base to ground and with the feedback necessary for
oscillation provided by a capacitor tap at the emitter. The
arrangement is shown inset in Fig. 5.
C1 C2
FROM
CHARGE
PUMP
OUTPUT
FROM
CHARGE
PUMP
REFERENCE
R2
-
TO
+ VCO
Fig. 8 third order loop filter circuit diagram
Loop Filter Design
Generally the third order filter configuration shown in Fig.8
gives better results than the more commonly used second
order because the reference sidebands are reduced. Three
equations are required to determine values for the three
constants where;
τ1 = C1
τ2 = R2 (C1 + C2)
τ3 = C2 R2
The equations are
1
τ1
=
Kφ K0
Nωn2
1 + ωn2 τ22
1 + ωn2 τ32
1/2
2
τ2 =
1
ωn2 τ3
3
τ3 =
-
tan
φο
+
1
cos
φο
ωn
Where;
Kφ is the phase detector gain factor in mA/radian
K0 is theVCO gain factor in radian/second/Volt
N is the total division ratio from VCO to reference
frequency
ωn is the natural loop bandwidth
φο is the phase margin normally set to 45°
Since the phase detector is linear over a range of 2π radian,
Kφ can be calculated from
Kφ = Phase comparator current setting/2π mA/radian
These values can now be substituted in equation 1 to obtain
a value for C1 and equation 2 and 3 used to determine values
for C2 and R2
EXAMPLE
Calculate values for a loop with the following parameters
Frequency to be synthesised:
Reference frequency
Division ratio
ωn natural loop frequency
K0 VCO gain factor
φ0 phase margin
Phase comparator current
1000MHz
10MHz
1000MHz/10MHz = 100
100KHz
2π x 10MHz/Volt
45°
6.3mA
The phase detector gain factor Kφ
= 6.3mA /2π = 1mA/radian
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet SP8855.PDF ] | |
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