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PDF MAX189 Data sheet ( Hoja de datos )
| Número de pieza | MAX189 | |
| Descripción | 1.4MHz SOT23 Current-Mode Step-Up DC-DC Converter | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MAX189 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
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19-0196; Rev 0; 10/93
EVFAOLLULAOTWIOSNDKAITTAMSAHNEUEATL
+5V, Low-Power, 12-Bit Serial ADCs
__________________General Description
The MAX187/MAX189 serial 12-bit analog-to-digital
converters (ADCs) operate from a single +5V supply
and accept a 0V to 5V analog input. Both parts feature
an 8.5µs successive-approximation ADC, a fast
track/hold (1.5µs), an on-chip clock, and a high-speed
3-wire serial interface.
The MAX187/MAX189 digitize signals at a 75ksps
throughput rate. An external clock accesses data from
the interface, which communicates without external
hardware to most digital signal processors and micro-
controllers. The interface is compatible with SPI™,
QSPI™, and Microwire™.
The MAX187 has an on-chip buffered reference, and
the MAX189 requires an external reference. Both the
MAX187 and MAX189 save space with 8-pin DIP and
16-pin SO packages. Power consumption is 7.5mW
and reduces to only 10µW in shutdown.
Excellent AC characteristics and very low power con-
sumption combined with ease of use and small pack-
age size make these converters ideal for remote DSP
and sensor applications, or for circuits where power
consumption and space are crucial.
___________________________Applications
Portable Data Logging
Remote Digital Signal Processing
Isolated Data Acquisition
High-Accuracy Process Control
________________Functional Diagram
________________________________Features
o 12-Bit Resolution
o ±1⁄2 LSB Integral Nonlinearity (MAX187A/MAX189A)
o Internal Track/Hold, 75kHz Sampling Rate
o Single +5V Operation
o Low Power: 2µA Shutdown Current
1.5mA Operating Current
o Internal 4.096V Buffered Reference (MAX187)
o 3-Wire Serial Interface, Compatible with SPI,
QSPI, and Microwire
o Small-Footprint 8-Pin DIP and 16-Pin SO
_________________Ordering Information
PART
MAX187ACPA
MAX187BCPA
MAX187CCPA
MAX187ACWE
MAX187BCWE
MAX187CCWE
MAX187BC/D
TEMP. RANGE
PIN-PACKAGE
ERROR
(LSB)
0°C to +70°C 8 Plastic DIP ±1⁄2
0°C to +70°C 8 Plastic DIP ±1
0°C to +70°C
0°C to +70°C
8 Plastic DIP
16 Wide SO
±2
±1⁄2
0°C to +70°C 16 Wide SO
±1
0°C to +70°C 16 Wide SO
±2
0°C to +70°C Dice*
±1
Ordering Information continued on last page.
* Dice are specified at TA = +25°C, DC parameters only.
** Contact factory for availability and processing to MIL-STD-883.
_________________Pin Configurations
5
GND
REF 4
2
AIN
1
VDD
+2.5V
BANDGAP
REF-
AV = 1.638
DAC
10k (4.096V)
REF+
REFERENCE
(MAX187 ONLY)
OUTPUT
SHIFT
REGISTER
12-BIT
SAR
T/H
MAX187
MAX189
COMPARATOR
BUFFER ENABLE/DISABLE CONTROL
AND
TIMING
6
DOUT
8
SCLK
7
CS
3
SHDN
NOTE: PIN NUMBERS SHOWN ARE FOR 8-PIN DIPs ONLY.
TOP VIEW
VDD 1
AIN 2
SHDN 3
REF 4
MAX187
MAX189
8 SCLK
7 CS
6 DOUT
5 GND
DIP
Pin Configurations continued on last page.
™ SPI and QSPI are trademarks of Motorola. Microwire is a trademark of National Semiconductor.
________________________________________________________________ Maxim Integrated Products 1
Call toll free 1-800-998-8800 for free samples or literature.
1 page  
+5V, Low-Power, 12-Bit Serial ADCs
TIMING CHARACTERISTICS
(VDD = +5.0V ±5%, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Track/Hold Acquisition Time
tACQ CS = high (Note 7)
1.5 µs
MAX18_ _C/E
20 150
SCLK Fall to Output Data Valid tDO CLOAD = 100pF
ns
MAX18_ _M
20 200
CS Fall to Output Enable
CS Rise to Output Disable
tDV CLOAD = 100pF
tTR CLOAD = 100pF
100 ns
100 ns
SCLK Clock Frequency
fSCLK
5 MHz
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Low to CS Fall
Setup Time
tCH
tCL
tCSO
100 ns
100 ns
50 ns
CS Pulse Width
tCS
500 ns
Note 1: Tested at VDD = +5V.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: MAX187—internal reference, offset nulled; MAX189–external +4.096V reference, offset nulled. Excludes reference errors.
Note 4: Guaranteed by design. Not subject to production testing.
Note 5: External load should not change during conversion for specified ADC accuracy.
Note 6: DC test, measured at 4.75V and 5.25V only.
Note 7: To guarantee acquisition time, tACQ is the maximum time the device takes to acquire the signal, and is also the minimum
time needed for the signal to be acquired.
_______________________________________________________________________________________ 5
5 Page 
+5V, Low-Power, 12-Bit Serial ADCs
10000
1000
MAX187
100
MAX189*
10
1 *REF CONNECTED TO VDD
0.1 1 10 100 1000 10000 100000
CONVERSIONS PER SECOND
Figure 6. Average Supply Current vs. Conversion Rate
3.0
2.5
2.0
1.5
1.0
0.5
0
0.0001 0.001 0.01
0.1
1
10
TIME IN SHUTDOWN (sec)
Figure 7. tWAKE vs. Time in Shutdown (MAX187 only)
____________________Serial Interface
Initialization After Power-Up and
Starting a Conversion
When power is first applied, it takes the fully dis-
charged 4.7µF reference bypass capacitor up to 20ms
to provide adequate charge for specified accuracy.
With SHDN not pulled low, the MAX187/MAX189 are
now ready to convert.
To start a conversion, pull CS low. At CS’s falling edge,
the T/H enters its hold mode and a conversion is initiat-
ed. After an internally timed 8.5µs conversion period,
the end of conversion is signaled by DOUT pulling
high. Data can then be shifted out serially with the
external clock.
Using SHDN to Reduce Supply Current
Power consumption can be reduced significantly by
shutting down the MAX187/MAX189 between conver-
sions. This is shown in Figure 6, a plot of average sup-
ply current vs. conversion rate. Because the MAX189
uses an external reference voltage (assumed to be pre-
sent continuously), it "wakes up" from shutdown more
quickly, and therefore provides lower average supply
currents. The wakeup-time, tWAKE, is the time from
SHDN deasserted to the time when a conversion may
be initiated. For the MAX187, this time is 2µs. For the
MAX189, this time depends on the time in shutdown
(see Figure 7) because the external 4.7µF reference
bypass capacitor loses charge slowly during shutdown
(see the specifications for shutdown, REF Input Current
= 10µA max).
External Clock
The actual conversion does not require the external
clock. This frees the µP from the burden of running the
SAR conversion clock, and allows the conversion result
to be read back at the µP’s convenience at any clock
rate from 0MHz to 5MHz. The clock duty cycle is unre-
stricted if each clock phase is at least 100ns. Do not
run the clock while a conversion is in progress.
Timing and Control
Conversion-start and data-read operations are con-
trolled by the CS and SCLK digital inputs. The timing
diagrams of Figures 8 and 9 outline the operation of the
serial interface.
A CS falling edge initiates a conversion sequence: The
T/H stage holds input voltage, the ADC begins to con-
vert, and DOUT changes from high impedance to logic
low. SCLK must be kept inactive during the conversion.
An internal register stores the data when the conversion
is in progress.
End of conversion (EOC) is signaled by DOUT going
high. DOUT’s rising edge can be used as a framing
signal. SCLK shifts the data out of this register any time
after the conversion is complete. DOUT transitions on
SCLK’s falling edge. The next falling clock edge pro-
duces the MSB of the conversion at DOUT, followed by
the remaining bits. Since there are 12 data bits and one
leading high bit, at least 13 falling clock edges are
needed to shift out these bits. Extra clock pulses occur-
ring after the conversion result has been clocked out,
and prior to a rising edge of CS, produce trailing 0s at
DOUT and have no effect on converter operation.
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet MAX189.PDF ] | |
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