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PDF MAX9159 Data sheet ( Hoja de datos )
| Número de pieza | MAX9159 | |
| Descripción | Dual LVDS Line Receiver | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MAX9159 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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19-2274; Rev 0; 1/02
Dual LVDS Line Receiver
General Description
The MAX9159 dual low-voltage differential signaling
(LVDS) receiver is ideal for applications requiring high
speed, low power, and low noise. The MAX9159 is pin
compatible with the SN65LVDS9637. The MAX9159
conforms to the ANSI TIA/EIA-644 LVDS standard and
converts LVDS to LVTTL-compatible outputs. A fail-safe
feature sets the output high when the inputs are undriv-
en and open, terminated, or shorted. The MAX9159 is
available in an 8-pin SO package and fully specified for
the -40°C to +85°C extended temperature range.
Refer to the MAX9111/MAX9113 data sheet for higher
performance single/dual LVDS line receivers in SOT23
and SO packages. Refer to the MAX9110/MAX9112
data sheet for single/dual LVDS line drivers in SOT23
and SO packages.
Applications
Network Switches/Routers
Telecom Switching Equipment
Cellular Phone Base Stations
Digital Copiers
LCD Displays
Backplane Interconnect
Clock Distribution
Features
o Pin Compatible with SN65LVDS9637
o Fail-Safe Circuit Sets Output High for Undriven
Inputs
o Conforms to ANSI TIA/EIA-644 Standard
o Single 3.3V Supply
o Designed for Data Rates up to 400Mbps
o ±100mV (max) Differential Input Threshold
o 2.2ns (typ) Propagation Delay
o 41mW (typ) Power Dissipation per Receiver at
200MHz
o ±8kV ESD Protection for LVDS Inputs
o Low-Voltage TTL (LVTTL) Logic Output Levels
PART
MAX9159ESA
Ordering Information
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
8 SO
Typical Operating Circuit
3.3V
DIN_ DRIVER
3.3V
0.001µF
0.1µF
_A
0.001µF
0.1µF
RT = 100Ω
RECEIVER
_Y
LVDS
_B
MAX9110
MAX9112
MAX9159
TOP VIEW
VCC 1
1Y 2
2Y 3
GND 4
Pin Configuration
MAX9159
SO
8 1A
7 1B
6 2A
5 2B
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
Dual LVDS Line Receiver
Typical Operating Characteristics (continued)
(VCC = 3.3V, |VID| = 200mV, VCM = 1.2V, fIN = 200MHz, CL = 10pF, TA = +25°C, unless otherwise noted.)
TRANSITION TIME vs. TEMPERATURE
0.6
0.5
tF
0.4
tR
0.3
0.2
-40
-15 10 35 60
TEMPERATURE (°C)
85
PROPAGATION DELAY
vs. LOAD CAPACITANCE
3.6
3.4
3.2
3.0
2.8 tPHL
2.6
2.4 tPLH
2.2
2.0
10 15 20 25 30 35 40 45 50
LOAD CAPACITANCE (pF)
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
10
TRANSITION TIME
vs. LOAD CAPACITANCE
tF
tR
15 20 25 30 35 40 45
LOAD CAPACITANCE (pF)
50
Pin Description
PIN NAME
FUNCTION
1 VCC Power Supply
2 1Y Channel 1 Output
3 2Y Channel 2 Output
4 GND Ground
5 2B Channel 2 Inverting Differential Input
6 2A Channel 2 Noninverting Differential Input
7 1B Channel 1 Inverting Differential Input
8 1A Channel 1 Noninverting Differential Input
Detailed Description
LVDS is intended for point-to-point communication over
a controlled-impedance medium as defined by the
ANSI TIA/EIA-644 and IEEE 1596.3 standards. LVDS
uses a lower voltage swing than other common commu-
nication standards, achieving higher data rates with
reduced power consumption, while reducing EMI
emissions and system susceptibility to noise.
The MAX9159 is a dual LVDS line receiver ideal for
applications requiring high data rates, low power, and
low noise. The device accepts an LVDS input and
translates it to an LVTTL output. The receiver detects
differential signals as low as 100mV and as high as
0.6V within an input voltage range of 0 to 2.4V.
The 250mV to 450mV differential output of an LVDS dri-
ver is nominally centered around a 1.25V offset. This
offset, coupled with the receiver’s 0 to 2.4V input volt-
age range, allows an approximate ±1V shift in the sig-
nal (as seen by the receiver). This allows for a
difference in ground references of the driver and the
receiver, the common-mode effects of coupled noise,
or both. The LVDS standards specify an input voltage
range of 0 to 2.4V referenced to receiver ground.
Fail-Safe
The fail-safe feature of the MAX9159 sets the output
high and reduces supply current when:
• Inputs are open.
• Inputs are undriven and shorted.
• Inputs are undriven and terminated.
A fail-safe circuit is important because under these
conditions, noise at the input may switch the receiver
and it may appear to the system that data is being
received. Open or undriven terminated input conditions
can occur when a cable is disconnected or cut, or
when an LVDS driver output is in high impedance. A
short condition can occur because of a cable failure.
The fail-safe input network (Figure 1) samples the input
common-mode voltage and compares it to VCC - 0.3V
(nominal). When the input is driven to levels specified in
the LVDS standards, the input common-mode voltage is
less than VCC - 0.3V and the fail-safe circuit is not acti-
_______________________________________________________________________________________ 5
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| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet MAX9159.PDF ] | |
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