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PDF MAX9158 Data sheet ( Hoja de datos )
| Número de pieza | MAX9158 | |
| Descripción | Quad Bus LVDS Transceiver in 44 QFN | |
| Fabricantes | Maxim Integrated | |
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19-2396; Rev 0; 4/02
Quad Bus LVDS Transceiver in 44 QFN
General Description
The MAX9158 is a quad bus LVDS (BLVDS) transceiver
for heavily loaded, half-duplex multipoint buses. A 44-
lead QFN package and flow-through pinout allow the
transceiver to be placed near the connector. The
MAX9158 drives LVDS levels into a 27Ω load (double
terminated, heavily loaded LVDS bus) at up to
200Mbps. An input fail-safe circuit ensures the receiver
output is high when the differential inputs are open, or
undriven and shorted, or undriven and terminated. The
MAX9158 operates from a single 3.3V supply, consum-
ing 77mA supply current with drivers enabled, and
19.9mA with drivers disabled.
The MAX9158’s high-impedance I/Os (except for receiver
outputs) when VCC = 0V or open, combined with glitch-
free power-up and power-down, allow hot swapping of
cards in multicard bus systems; 7.3pF (max) BLVDS I/O
capacitance minimizes bus loading.
The MAX9158 is offered in a 7mm ✕ 7mm 44-lead QFN
package, and is fully specified for the -40°C to +85°C
extended temperature range. Refer to the MAX9157 data
sheet for a quad BLVDS transceiver with hysteresis in 32-
lead QFN and TQFP packages. Refer to the MAX9129
data sheet for a quad BLVDS driver, ideal for dual multi-
point full-duplex buses.
Applications
Add/Drop Muxes
Digital Cross-Connects
Network
Switches/Routers
Cellular Phone Base
Stations
DSLAMs
Multipoint Buses
Features
o 44-Lead QFN Package
o 1ns (min) Driver Transition Time (0% to 100%)
Minimizes Reflections
o Guaranteed 7.3pF (max) Bus Load Capacitance
o Glitch-Free Power-Up and Power-Down
o Hot-Swappable, High-Impedance I/O with VCC =
0V or Open
o Guaranteed 200Mbps Driver Data Rate
o Low-Jitter Fail-Safe Circuit
o Flow-Through Pinout
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
MAX9158EGM -40°C to +85°C 44 QFN (7mm ✕ 7mm)
Pin Configuration
TOP VIEW
(LEADS UNDER PACKAGE)
N.C.
N.C.
VCC
GND
RE34
VCC
AVCC
DE34
AGND
AVCC
N.C.
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
MAX9158EGM
34 N.C.
33 N.C.
32 N.C.
31 GND
30 VCC
29 RE12
28 GND
27 AVCC
26 DE12
25 AGND
24 N.C.
23 N.C.
Functional Diagram appears at end of data sheet.
MAX9158
CARD 1
MAX9158
CARD 15
QFN
Typical Operating Circuit
MAX9158
CARD 16
1in CARD
SPACING
Rt = 54Ω
Rt = 54Ω
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
Quad Bus LVDS Transceiver in 44 QFN
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.0V to 3.6V, RL = 27Ω ±1%, receiver differential input voltage |VID| = 0.15V to VCC, receiver input voltage range = 0V to VCC, input
frequency to differential inputs = 100MHz, input frequency to LVCMOS/LVTTL inputs = 100MHz, LVCMOS/LVTTL inputs = 0V to VCC with
2ns (10% to 90%) transition times. Differential input voltage transition time = 1ns (20% to 80%). Receiver input common-mode voltage
VCM = 0.075V to 2.4V, DE_ = high, RE_ = low, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3V, |VID| =
0.2V, VCM = 1.2V, and TA = +25°C.) (Notes 3 and 5)
PARAMETER
Fall Time
Disable Time High to Z
SYMBOL
tTHL
tPHZ
CONDITIONS
DE_ = low, Figures 7, 8, CL = 15pF
DE_ = low, RL = 500Ω, CL = 15pF,
Figures 9, 10
MIN TYP MAX UNITS
0.7 1.24 1.8
ns
6.0 8
ns
Disable Time Low to Z
tPLZ
DE_ = low, RL = 500Ω, CL = 15pF,
Figures 9, 10
6.5 8
ns
Enable Time Z to High
tPZH
DE_ = low, RL = 500Ω, CL = 15pF,
Figures 9, 10
4.3 7
ns
Enable Time Z to Low
tPZL
DE_ = low, RL = 500Ω, CL = 15pF,
Figures 9, 10
4.3 7
ns
Maximum Operating Frequency
(Note 10)
fMAX DE_ = low, CL = 15pF
100 MHz
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except VTH, VTL, VID, VOD, and ∆VOD.
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at TA = +25°C.
Note 3: Guaranteed by design and characterization.
Note 4: Short only one output at a time. Do not exceed the absolute maximum junction temperature specification.
Note 5: CL includes scope probe and test fixture capacitance.
Note 6: tSKD1 is the magnitude difference of differential propagation delays in a channel. tSKD1 = | tPHLD - tPLHD |.
Note 7: tCCSK is the magnitude difference of the tPLHD or tPHLD of one channel and the tPLHD or tPHLD of any other channel on the
same part.
Note 8: tSKD2 is the magnitude difference of any differential propagation delays between parts operating over rated conditions at
the same VCC and within 5°C of each other.
Note 9: tSKD3 is the magnitude difference of any differential propagation delays between parts operating over rated conditions.
Note 10: Meets data sheet specifications while operating at minimum fMAX rating.
_______________________________________________________________________________________ 5
5 Page 
Quad Bus LVDS Transceiver in 44 QFN
DIN_
DO_-/RIN_-
DO_+/RIN_+
50%
tPLHD
0V DIFFERENTIAL
50%
tPHLD
VCC
0V
VOH
0V
VOL
VOD 20%
80% 80%
0V
VOD = (VDO_+/RIN_+ - VDO_-/RIN_-)
0V
20%
tTLH tTHL
Figure 4. Driver Propagation Delay and Transition Time
Waveforms
VCC
GND
GENERATOR
50Ω
DIN_
DE_
1/4 MAX9158
CL
DO_+/RIN_+
RL/2
+1.2V
RL/2
DO_-/RIN_-
CL
Figure 5. Driver High-Impedance Delay Test Circuit
DE_
D0_+/RIN_+ WHEN DIN_ = VCC
DO_-/RIN_- WHEN DIN_ = 0V
50%
tPHZ
50%
DO_+/RIN_+ WHEN DIN_ = 0V
DO_-/RIN_- WHEN DIN_ = VCC
Figure 6. Driver High-Impedance Delay Waveform
50%
tPLZ
50%
tPZH
50%
50%
tPZL
VCC
0V
VOH
1.2V
1.2V
VOL
PULSE
GENERATOR
DO_+/RIN_+
DO_-/RIN_-
RO_
CL
50Ω*
50Ω*
RECEIVER ENABLED
1/4 MAX9158
*50Ω REQUIRED FOR PULSE GENERATOR TERMINATION.
Figure 7. Receiver Transition Time and Propagation Delay Test Circuit
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet MAX9158.PDF ] | |
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