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PDF MAX5888 Data sheet ( Hoja de datos )
| Número de pieza | MAX5888 | |
| Descripción | 3.3V / 16-Bit / 500Msps High Dynamic Performance DAC with Differential LVDS Inputs | |
| Fabricantes | Maxim Integrated | |
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19-2726; Rev 3; 12/03
3.3V, 16-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
General Description
The MAX5888 is an advanced, 16-bit, 500Msps digital-
to-analog converter (DAC) designed to meet the
demanding performance requirements of signal synthe-
sis applications found in wireless base stations and
other communications applications. Operating from a
single 3.3V supply, this DAC offers exceptional dyna-
mic performance such as 76dBc spurious-free dynamic
range (SFDR) at fOUT = 40MHz. The DAC supports
update rates of 500Msps and a power dissipation of
only 250mW.
The MAX5888 utilizes a current-steering architecture,
which supports a full-scale output current range of 2mA
to 20mA, and allows a differential output voltage swing
between 0.1VP-P and 1VP-P.
The MAX5888 features an integrated 1.2V bandgap ref-
erence and control amplifier to ensure high accuracy
and low noise performance. Additionally, a separate
reference input pin enables the user to apply an exter-
nal reference source for optimum flexibility and to
improve gain accuracy.
The digital and clock inputs of the MAX5888 are
designed for differential low-voltage differential signal
(LVDS)-compatible voltage levels. The MAX5888 is
available in a 68-lead QFN package with an exposed
paddle (EP) and is specified for the extended industrial
temperature range (-40°C to +85°C).
Refer to the MAX5887 and MAX5886 data sheets for
pin-compatible 14- and 12-bit versions of the MAX5888.
Applications
Base Stations: Single-/Multicarrier UMTS,
CDMA, GSM
Communications: LMDS, MMDS, Point-to-Point
Microwave
Digital Signal Synthesis
Automated Test Equipment (ATE)
Instrumentation
Features
o 500Msps Output Update Rate
o Single 3.3V Supply Operation
o Excellent SFDR and IMD Performance
SFDR = 76dBc at fOUT = 40MHz (to Nyquist)
IMD = -85dBc at fOUT = 10MHz
ACLR = 73dB at fOUT = 61MHz
o 2mA to 20mA Full-Scale Output Current
o Differential, LVDS-Compatible Digital and Clock
Inputs
o On-Chip 1.2V Bandgap Reference
o Low 130mW Power Dissipation
o 68-Lead QFN-EP Package
Ordering Information
PART
TEMP RANGE
MAX5888AEGK
-40°C to +85°C
MAX5888EGK
-40°C to +85°C
*EP = Exposed paddle.
PIN-
PACKAGE
68 QFN-EP*
68 QFN-EP*
Pin Configuration
TOP VIEW
B3P 1
B3N 2
B2P 3
B2N 4
B1P 5
B1N 6
B0P 7
B0N 8
DGND 9
DVDD 10
VCLK 11
CLKGND 12
CLKP 13
CLKN 14
CLKGND 15
VCLK 16
PD 17
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
EP
MAX5888
51 B11N
50 B11P
49 B12N
48 B12P
47 B13N
46 B13P
45 B14N
44 B14P
43 B15N
42 B15P
41 DGND
40 DVDD
39 SEL0
38 N.C.
37 N.C.
36 N.C.
35 N.C.
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
QFN
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
3.3V, 16-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, VREFIO = 1.25V, differential transformer-coupled
analog output, 50Ω double terminated (Figure 7), IOUT = 20mA, TA = TMIN to TMAX, unless otherwise noted. ≥+25°C guaranteed by
production test, <+25°C guaranteed by design and characterization. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Power Dissipation
Power-Supply Rejection Ratio
PDISS
fCLK = 100Msps, fOUT = 1MHz
Power-down
130
mW
1
PSRR AVDD = VCLK = DVDD = 3.3V ±5% (Note 6)
-1
+1 %FS/V
Note 1: Nominal full-scale current IOUT = 32 ✕ IREF.
Note 2: This parameter does not include update-rate depending effects of sin(x)/x filtering inherent in the MAX5888.
Note 3: Parameter measured single ended into a 50Ω termination resistor.
Note 4: Parameter guaranteed by design.
Note 5: A differential clock input slew rate of >100V/ms is required to achieve the specified dynamic performance.
Note 6: Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.
Typical Operating Characteristics
(AVDD = DVDD = VCLK = 3.3V, external reference, VREFIO = 1.25V, RL = 50Ω, IOUT = 20mA, TA = +25°C, unless otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 100MHz)
100
90 -12dB FS
80
70
60 -6dB FS
50
0dB FS
40
30
20
10
0
0 10 20 30 40 50
fOUT (MHz)
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 200MHz)
100
90 -6dB FS
80
70
60
-12dB FS
50
0dB FS
40
30
20
10
0
0 10 20 30 40 50 60 70 80 90 100
fOUT (MHz)
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 500MHz)
100
90
80
70
-6dB FS
-12dB FS
60
50
40
30 0dB FS
20
10
0
0 50 100 150 200 250
fOUT (MHz)
2-TONE INTERMODULATION DISTORTION
(fCLK = 100MHz)
0
-10
AOUT = -6dB FS
BW = 5MHz
fT1 = 9.0252MHz
fT2 = 10.0417MHz
-20
-30 fT1 fT2
-40
-50
-60
-70
-80 2 x fT1 - fT2
2 x fT2 - fT1
-90
-100
7 8 9 10 11 12
fOUT (MHz)
2-TONE IMD vs. OUTPUT FREQUENCY
(1MHz CARRIER SPACING, fCLK = 300MHz)
-100
-90
-12dB FS
-80
-70
-60
-6dB FS
-50
-40
0
25 50 75 100
fOUT (MHz)
2-TONE INTERMODULATION DISTORTION
(fCLK = 450MHz)
0
-10
AOUT = -6dB FS
BW = 5MHz
fT1 = 79.2114MHz
fT2 = 80.0903MHz
-20
-30 fT1 fT2
-40
-50
-60 2 x fT1 - fT2
-70
2 x fT2 - fT1
-80
-90
-100
77 78 79 80 81 82
fOUT (MHz)
_______________________________________________________________________________________ 5
5 Page 
3.3V, 16-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
B0 TO B15
DIGITAL DATA IS LATCHED ON OUTPUT DATA IS UPDATED ON
THE RISING EDGE OF CLKP
THE FALLING EDGE OF CLKP
N-1 N
N+1 N+2
tSETUP
tHOLD
tCH tCL
CLKP
CLKN
IOUT N - 5
tPD
N-4
Figure 5. Detailed Timing Relationship
N-3
N-2 N-1
frequencies. Their differential characteristic supports
the transmission of high-speed data patterns without
the negative effects of electromagnetic interference
(EMI). All MAX5888 LVDS inputs feature on-chip termi-
nation with differential 100Ω resistors. See Figure 6 for
a simplified block diagram of the LVDS inputs.
A common-mode level of 1.25V and an 800mV differen-
tial input swing can be applied to these inputs.
Segment Shuffling (SEL0)
Segment shuffling can improve the SFDR of the
MAX5888. The improvement is most pronounced at
higher output frequencies and amplitudes. Note that an
improvement in SFDR can only be achieved at the cost
of a slight increase in the DAC’s noise floor.
Pin SEL0 controls the segment-shuffling function. If
SEL0 is pulled low, the segment-shuffling function of
the DAC is disabled. SEL0 can also be left open,
because an internal pulldown resistor helps to deacti-
vate the segment-shuffling feature. To activate the
MAX5888 segment-shuffling function, SEL0 must be
pulled high.
Power-Down Operation (PD)
The MAX5888 also features an active-high power-down
mode, which allows the user to cut the DAC’s digital
current consumption to less than 6µA and the analog
current consumption to less than 0.3mA. A single pin
(PD) is used to control the power-down mode (PD = 1)
or reactivate the DAC (PD = 0) after power-down.
B0P–B15P
100Ω
B0N–B15N
DQ
DQ
CLOCK
TO DECODE
LOGIC
Figure 6. Simplified LVDS-Compatible Input Structure
Enabling the power-down mode of the MAX5888 allows
the overall power consumption to be reduced to less
than 1mW. The MAX5888 requires 10ms to wake up
from power-down and enter a fully operational state.
Applications Information
Differential Coupling Using a
Wideband RF Transformer
The differential voltage existing between IOUTP and
IOUTN can also be converted to a single-ended volt-
age using a transformer (Figure 7) or a differential
amplifier configuration. Using a differential transformer
coupled output, in which the output power is limited to
0dBm, can optimize the dynamic performance.
However, make sure to pay close attention to the trans-
former core saturation characteristics when selecting a
transformer for the MAX5888. Transformer core satura-
tion can introduce strong 2nd-harmonic distortion,
especially at low output frequencies and high signal
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet MAX5888.PDF ] | |
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