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PDF MAX503 Data sheet ( Hoja de datos )
| Número de pieza | MAX503 | |
| Descripción | 5V / Low-Power / Parallel-Input / Voltage-Output / 10-Bit DAC | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MAX503 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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19-0279; Rev 0; 8/94
5V, Low-Power, Parallel-Input,
Voltage-Output, 10-Bit DAC
_______________General Description
The MAX503 is a low-power, 10-bit, voltage-output digital-
to-analog converter (DAC) that uses single 5V or dual ±5V
supplies. This device has an internal voltage reference plus
an output buffer amplifier. Operating current is only 250µA
from a single 5V supply, making it ideal for portable and
battery-powered applications. In addition, the shrink small-
outline package (SSOP) measures only 0.1 square inches,
using less board area than an 8-pin DIP. 10-bit resolution is
achieved through laser trimming of the DAC, op amp, and
reference. No further adjustments are necessary.
Internal gain-setting resistors can be used to define a DAC
output voltage range of 0V to +2.048V, 0V to +4.096V, or
±2.048V. Four-quadrant multiplication is possible without
the use of external resistors or op amps. The parallel logic
inputs are double buffered and are compatible with 4-bit, 8-
bit, and 16-bit microprocessors. For a hardware and soft-
ware compatible 12-bit upgrade, refer to the MAX530 data
sheet. For DACs with similar features but with a serial data
interface, refer to the MAX504/MAX515 data sheet.
________________________Applications
Battery-Powered Data-Conversion Products
Minimum Component-Count Analog Systems
Digital Offset/Gain Adjustment
Industrial Process Control
Arbitrary Function Generators
Automatic Test Equipment
Microprocessor-Controlled Calibration
________________Functional Diagram
REFGND
AGND
17
14
15
CLR
A0 8
A1 9
CS 11
WR 10
LDAC 16
REFOUT
18
2.048V
REFERENCE
REFIN ROFS
13 22
POWER-ON
RESET
DAC
MAX503
10D-BAICT DLATCCLHATCH
21 RFB
20 VOUT
23 VDD
12 DGND
19 VSS
CONTROL
LOGIC
NBL
INPUT
LATCH
NBM
INPUT
LATCH
NBH
INPUT
LATCH
24 1 2 3 4 5 6 7
D6/S0 D8/D0 D2 D4
D7/S1 D9/D1 D3 D5
____________________________Features
o Buffered Voltage Output
o Internal 2.048V Voltage Reference
o Operates from Single 5V or Dual ±5V Supplies
o Low Power Consumption:
250µA Operating Current
40µA Shutdown-Mode Current
o SSOP Package Saves Space
o Relative Accuracy: ±1/2 LSB Max Over
Temperature
o Guaranteed Monotonic Over Temperature
o 4-Quadrant Multiplication with No External
Components
o Power-On Reset
o Double-Buffered Parallel Logic Inputs
______________Ordering Information
PART
MAX503CNG
MAX503CWG
MAX503CAG
MAX503ENG
MAX503EWG
MAX503EAG
TEMP. RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
24 Narrow Plastic DIP
24 Wide SO
24 SSOP
24 Narrow Plastic DIP
24 Wide SO
24 SSOP
Refer to the MAX530 for military temperature or die equivalents.
__________________Pin Configuration
TOP VIEW
D7/S1 1
D8/D0 2
D9/D1 3
D2 4
D3 5
D4 6
D5 7
A0 8
A1 9
WR 10
CS 11
DGND 12
MAX503
24 D6/S0
23 VDD
22 ROFS
21 RFB
20 VOUT
19 VSS
18 REFOUT
17 REFGND
16 LDAC
15 CLR
14 AGND
13 REFIN
DIP/SO/SSOP
________________________________________________________________ Maxim Integrated Products 1
Call toll free 1-800-998-8800 for free samples or literature.
1 page  
5V, Low-Power, Parallel-Input,
Voltage-Output, 10-Bit DAC
__________________________________________Typical Operating Characteristics
(Single +5V supply, unity gain, code = all 1s, TA = +25°C, unless otherwise noted.)
OUTPUT SINK CAPABILITY vs.
OUTPUT PULL-DOWN VOLTAGE
16
14
12
10
8
6
4
2
0
0
0.2 0.4 0.6 0.8 1.0
OUTPUT PULL-DOWN VOLTAGE (V)
OUTPUT SOURCE CAPABILITY vs.
OUTPUT PULL-UP VOLTAGE
8
7
6
5
4
3
2
1
0
0
1 234
OUTPUT PULL-UP VOLTAGE (V)
5
ANALOG FEEDTHROUGH vs.
FREQUENCY
-110
-100
-90
-80
-70 REFIN = 2Vp-p
-60
-50
-40
-30
-20
-10
0
1
CODE = ALL 0s,
DUAL SUPPLIES (±5V)
10 100 1k 10k
100k
FREQUENCY (Hz)
1M
2.055
REFERENCE VOLTAGE vs.
TEMPERATURE
2.050
2.045
-60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
SUPPLY CURRENT vs. TEMPERATURE
300
290
280
270
260
250
240
230
-60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
4
2
0
-2
-4
-6
-8
-10
-12
-14
1
GAIN vs. FREQUENCY
REFIN = 4Vp-p
DUAL SUPPLIES (±5V)
100 1k 10k
FREQUENCY (Hz)
100k
AMPLIFIER SIGNAL-TO- NOISE RATIO
80
REFIN = 4Vp-p
70
60
50
40
30
DUAL SUPPLIES (±5V)
20
10
0
10
100 1k 10k
FREQUENCY (Hz)
100k
200
100
0
-100
-200
-300
1
GAIN AND PHASE vs.
FREQUENCY
(G = 2)
(G = 1)
GAIN
180
PHASE
0
10 100
FREQUENCY (kHz)
-180
800
_______________________________________________________________________________________ 5
5 Page 
5V, Low-Power, Parallel-Input,
Voltage-Output, 10-Bit DAC
A0–A1
CS
WR
DATA BITS
(8-BIT BYTE
OR 4-BIT NIBBLE)
CLR
ADDRESS BUS VALID
VIH
VIL
tAWH
tCWS
tAWS
tWR
tCWH
tDS tDH
VIH
VIL
DATA BUS
VALID
tCLR
LDAC
NOTE:
TIMING MEASUREMENT REFERENCE LEVEL IS
VIH + VIL
2
tLDAC
Figure 4. MAX503 Write-Cycle Timing Diagram
A small error voltage is added to the reference output
by the reference current flowing through the N-channel
pull-down transistor. The switch’s on resistance should
be less than 5Ω. A typical reference current of 100µA
would add 0.5mV to REFOUT. Since the reference cur-
rent and on resistance increase with temperature, the
overall temperature coefficient will degrade slightly.
As data is loaded into the DAC and the output moves
above GND, the op-amp quiescent current increases to
its nominal value and the total operating current aver-
ages 250µA. Using dual supplies (±5V), the op amp is
fully biased continuously, and the VDD supply current is
more constant at 250µA. The VSS current is typically
150µA.
The MAX503 logic inputs are compatible with TTL and
CMOS logic levels. However, to achieve the lowest
power dissipation, drive the digital inputs with rail-to-rail
CMOS logic. With TTL logic levels, the power require-
ment increases by a factor of approximately 2.
Parallel Logic Interface
In order to provide hardware and software compatibility
with the 12-bit MAX530, the MAX503 employs a 12-bit
digital interface. As shown in Figure 3, there is actually
a 12-bit input latch, and therefore 12 bits of data should
be written. The two least significant bits (S1 and S0) are
sub-LSB, and must always be 0s. Designed to interface
with 4-bit, 8-bit, and 16-bit microprocessors (µPs), the
MAX503 uses 8 data pins and double-buffered logic
inputs to load data as 4 + 4 + 4 or 8 + 4. The 12-bit
DAC latch is updated simultaneously through the con-
trol signal LDAC. Signals A0, A1, WR, and CS select
which input latches to update. The 12-bit data is bro-
ken down into nibbles (NB); NBL is the enable signal
for the lowest 4 bits (S0, S1, D0, D1), NBM is the
enable for the middle 4 bits, and NBH is the enable for
the highest and most significant 4 bits. Table 2 lists the
address decoding scheme.
Refer to Figure 4 for the MAX503 write-cycle timing
diagram.
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet MAX503.PDF ] | |
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