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PDF PI6C9911J Data sheet ( Hoja de datos )
| Número de pieza | PI6C9911J | |
| Descripción | 5V High-Speed Programmable Skew Clock Buffers | |
| Fabricantes | ETC | |
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Hay una vista previa y un enlace de descarga de PI6C9911J (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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PI6C9911 & PI6C9911E111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222
5V High-Speed Programmable Skew
Clock Buffers - SuperClock®
Product Features
• Four pairs of programmable skew outputs
• User-selectable output functions:
− Selectable skews
− Inverted and noninverted
− Operation at ½ and ¼ input frequency
− Operation at 2X and 4X input frequency
• Low skew <100ps typical same pair, 250ps max.
• Allow REF clock input to have Spread Spectrum
modulation for EMI reduction
• 2X, 4X, ½ and ¼ outputs
• 3-level inputs for skew and output frequency control
• External feedback, internal loop filter
• Low cycle-to-cycle Jitter: <25ps RMS
• Duty cycle of output clock signals: 45% min. 55% max.
• Same pinout as Cypress CY7B9911
• Available in 32-pin PLCC Package (J)
• Output Operation
3.75 to 100 MHz for PI6C9911
3.75 to 125 MHz for PI6C9911E
Description
The PI6C9911 and PI6C9911E are low-skew, low jitter, 5V phase-
lock-loop (PLL) programmable skew clock drivers, for
high-performance computing and networking applications. These
parts offer user-selectable skew-control of 4 output pairs, provid-
ing the timing delays necessary to optimize high-performance
clock-distribution circuits.
Each output can be hardwired to one of nine delay or function
configurations. Delay increments are determined by the input clock
frequency and the configurations selected by the user.
The PI6C9911 and PI6C9911E allow the REF clock input to have
Spread Spectrum modulation for EMI reduction.
Both buffers are pin-compatable with Cypresss RoboClock
CY7B9911, but with improved AC/DC characteristics.
The PI6C9911 and PI6C9911E also have the same pinout as
Cypresss CY7B9911and with balanced output drive.
Logic Block Diagram
TEST
FB Phase
REF
Freq
Det
Filter
FS
4F0
4F1
3F0
3F1
Three Level
Select Inputs
2F0
2F1
1F0
1F1
Vco and
Time Unit
Generator
SKEW
SELECT
MATRIX
Pin Configuration
4 3 2 1 32 31 30
3F1 5
29
2F0
4F0 6
28 GND
4Q0 4F1 7
27 1F1
4Q1
VCCQ 8
32-Pin
26 1F0
J
3Q0 VCCN 9
25 VCCN
3Q1 4Q1 10
4Q0 11
2Q0 GND 12
24 1Q0
23 1Q1
22 GND
2Q1 GND 13
21 GND
14 15 16 17 18 19 20
1Q0
1Q1
1 PS8451B 03/28/01
1 page  
PI6C9911 & PI6C9911E
5V High Speed Programmable Skew
®
Clock Buffers - SuperClock111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222
DC Characteristics Over the Operating Range
Symbol
Parameter
Test Condition
Min.
Max. Units
VOH
VOL
VIH
VIL
VIH3
VIM3
VIL3
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage of REF, FB inputs
Input LOW Voltage of REF, FB inputs
Input HIGH Voltage of 3-level inputs
TEST, FS, xFn(6)
Input MID Voltage of 3-level inputs
TEST, FS, xFn(6)
Input LOW Voltage of 3-level inputs
TEST, FS, xFn(6)
Vcc = Min., IOH = –16mA
Vcc = Min., IOL = 46mA
Min ≤VCC ≤ Max
2.4
2.0
–0.5
VCC–0.85V
VCC/2 –0.5
0.45
VCC
0.8
VCC
VCC/2
+0.5
0.85
V
IIN Input Leakage Current of REF, FB inputs VIN = VCC or GND, VCC = Max
I3
3-Level Input DC Current
(TEST, FS, nF 1:0)
VIN = VCC (HIGH level)
VIN = VCC/2 (MID level)
VIN = GND (LOW level)
IOS Short Circuit Current
VCC = Max. VOUT = GND (25°
only)
ICCQ
Operating Current usd by Internal
Circuitry
VCCN = VCCQ = Max.
All Inputs Select Open
ICCN Output Buffer Current per Output Pair
PD Power Dissipation per Output Pair
VCCN = VCCQ = Max, IOUT = 0mA
Input Selects Open, fMAX
10
200
50
200
–250
85
14
78
µΑ
mA
mW
Capacitance at REF and FB
Parameter
Description
CIN Input Capacitance
Test Conditions
TA = 25ºC, f = 1 MHz, VCC = 5.0V
Max.
10
Units
pF
AC Test Loads and Waveforms (PI6C9911)
5V
R1 R1 = 130Ω
R2 = 91Ω
CL = 30pF
CL
R2
(Includes fixture
and probe capacitance)
TTL AC Test Load(16)
2.0V
Vth = 1.5V
0.8V
0.0V
≤1ns
3.0V
2.0V
Vth = 1.5V
0.8V
≤1ns
TTL Input Test Waveform
5 PS8451B 03/28/01
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet PI6C9911J.PDF ] | |
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