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PDF MAX107 Data sheet ( Hoja de datos )
| Número de pieza | MAX107 | |
| Descripción | Dual / 6-Bit / 400Msps ADC with On-Chip / Wideband Input Amplifier | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MAX107 (archivo pdf) en la parte inferior de esta página. Total 21 Páginas | ||
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19-2007; Rev 0; 5/01
Dual, 6-Bit, 400Msps ADC with On-Chip,
Wideband Input Amplifier
General Description
The MAX107 is a dual, 6-bit, analog-to-digital converter
(ADC) designed to allow fast and precise digitizing of in-
phase (I) and quadrature (Q) baseband signals. The
MAX107 converts the analog signals of both I and Q
components to digital outputs at 400Msps while achiev-
ing a signal-to-noise ratio (SNR) of typically 37dB with
an input frequency of 125MHz, and an integral nonlin-
earity (INL) and differential nonlinearity (DNL) of ±0.25
LSB. The MAX107 analog input preamplifiers feature a
400MHz, -0.5dB, and a 1.5GHz, -3dB analog input
bandwidth. Matching channel-to-channel performance
is typically 0.04dB gain, 0.1LSB offset, and 0.2 degrees
phase. Dynamic performance is 36.7dB signal-to-noise
plus distortion (SINAD) with a 125MHz analog input sig-
nal and a sampling speed of 400MHz. A fully differential
comparator design and encoding circuits reduce out-of-
sequence errors, and ensure excellent metastable per-
formance of only one error per 1016 clock cycles.
In addition, the MAX107 provides LVDS digital outputs
with an internal 6:12 demultiplexer that reduces the out-
put data rate to one-half the sample clock rate. Data is
output in two’s complement format. The MAX107 oper-
ates from a +5V analog supply and the LVDS output
ports operate at +3.3V. The data converter’s typical
power dissipation is 2.6W. The device is packaged in
an 80-pin, TQFP package with exposed paddle, and is
specified for the extended (-40°C to +85°C) tempera-
ture range. For a higher-speed, 800Msps version of the
MAX107, please refer to the MAX105 data sheet.
VSAT Receivers
WLANs
Test Instrumentation
Communications Systems
Applications
Features
o Two Matched 6-Bit, 400Msps ADCs
o Excellent Dynamic Performance
36.7dB SINAD at fIN ≈ 125MHz and
fCLK ≈ 400MHz
o Typical INL and DNL: ±0.25LSB
o Channel-to-Channel Phase Matching: ±0.2°
o Channel-to-Channel Gain Matching: ±0.04dB
o 6:12 Demultiplexer reduces the Data Rates to
200MHz
o Low Error Rate: 1016 Metastable States at
400Msps
o LVDS Digital Outputs in Two’s Complement
Format
PART
MAX107ECS
Ordering Information
TEMP. RANGE
-40°C to +85°C
PIN-PACKAGE
80-Pin TQFP-EP
Block Diagram
I ADC
I
PRIMARY
PORT
I
AUXILIARY
PORT
MAX107
REF
Pin Configuration appears at end of data sheet.
Q ADC
Q
PRIMARY
PORT
Q
AUXILIARY
PORT
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
Dual, 6-Bit, 400Msps ADC with On-Chip,
Wideband Input Amplifier
ELECTRICAL CHARACTERISTICS (continued)
(AVCC = AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ
= 0, fCLK = 401.408MHz, CL = 1µF to AGND at REF, RL = 100Ω ±1% applied to digital LVDS outputs, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C)
PARAMETER
DREADY Duty Cycle
LVDS Output Rise-Time
LVDS Output Fall-Time
LVDS Differential Skew
DREADY Rise-Time
DREADY Fall-Time
Primary Port Pipeline Delay
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
(Notes 5, 13)
47 53 %
tRDATA 20% to 80% (Notes 5, 13)
200 500
tFDATA 20% to 80% (Notes 5, 13)
200 500
tSKEW1
Any differential pair
Any two LVDS output signals except DREADY
<65
<100
ps
ps
ps
tRDREADY
tFDREADY
20% to 80% (Notes 5, 13)
20% to 80% (Notes 5, 13)
200 500 ps
200 500 ps
tPDP
5
Clock
Cycles
Auxiliary Port Pipeline Delay
tPDA
6
Clock
Cycles
Note 1: INL and DNL is measured using a sine-histogram method.
Note 2: Input offset is the voltage required to cause a transition between codes 0 and -1.
Note 3: Numbers provided are for DC-coupled case. The user has the choice of AC-coupling, in which case, the DC input voltage
level does not matter.
Note 4: The peak-to-peak input voltage required, causing a full-scale digitized output when using a trigonometric curve-fitting algo
rithm (e.g. FFT).
Note 5: Guaranteed by design and characterization.
Note 6: Common-mode rejection ratio is defined as the ratio of the change in the offset voltage to the change in the common-mode
voltage expressed in dB.
Note 7: Measured with analog power supplies tied to the same potential.
Note 8: Effective number of bits (ENOB) is computed from a curve-fit referenced to the theoretical full-scale range.
Note 9: The clock and input frequencies are chosen so that there are 2041 cycles in an 8,192-long record.
Note 10: Signal-to-noise-ratio (SNR) is measured both with the other channel idling and converting an out-of-phase signal.
The worst case number is presented. Harmonic distortion components two through five are excluded from the noise.
Note 11: Harmonic distortion components two through five are included in the total harmonic distortion specification.
Note 12: Both I and Q inputs are effectively tied together (e.g. driven by power splitter). Signal amplitude is -0.5dB FS at an input
frequency of fIN = 124.999 MHz.
Note 13: Measured with a differential probe, 1pF capacitance.
_______________________________________________________________________________________ 5
5 Page 
Dual, 6-Bit, 400Msps ADC with On-Chip,
Wideband Input Amplifier
PIN
62
63
64
65, 72
66, 71
67
68
69
70
73
74
75
76
77
78
79
80
NAME
P2I+
A2I-
A2I+
OVCCI
OGNDI
P3I-
P3I+
A3I-
A3I+
P4I-
P4I+
A4I-
A4I+
P5I-
P5I+
A5I-
A5I+
Pin Description (continued)
FUNCTION
Primary Output Data Bit 2, I-Channel
Complementary Auxiliary Output Data Bit 2, I-Channel
Auxiliary Output Data Bit 2, I-Channel
I-Channel Outputs, Digital Supply. Supplies I-channel output drivers and DREADY circuit. Bypass to
OGND with 0.01µF in parallel with 47pF for proper operation.
I-Channel Outputs, Digital Ground. Connect to designated digital ground (OGND) on PC board
for proper operation.
Complementary Primary Output Data Bit 3, I-Channel
Primary Output Data Bit 3, I-Channel
Complementary Auxiliary Output Data Bit 3, I-Channel
Auxiliary Output Data Bit 3, I-Channel
Complementary Primary Output Data Bit 4, I-Channel
Primary Output Data Bit 4, I-Channel
Complementary Auxiliary Output Data Bit 4, I-Channel
Auxiliary Output Data Bit 4, I-Channel
Complementary Primary Output Data Bit 5, I-Channel
Primary Output Data Bit 5, I-Channel
Complementary Auxiliary Output Data Bit 5, I-Channel
Auxiliary Output Data Bit 5, I-Channel
Detailed Description
The MAX107 is a dual, +5V, 6-bit, 400Msps flash ana-
log-to-digital converter (ADC), designed for high-speed,
high bandwidth I&Q digitizing. Each ADC (Figure 1)
employs a fully differential, wide bandwidth input stage,
6-bit quantizers and a unique encoding scheme to limit
metastable states to typically one error per 1016 clock
cycles, with no error exceeding a maximum of 1LSB. An
integrated 6:12 output demultiplexer simplifies interfac-
ing to the part by reducing the output data rate to one-
half the sampling clock rate. The MAX107 outputs data
in LVDS two’s complement format.
When clocked at 400Msps, the MAX107 provides a typ-
ical signal-to-noise plus distortion (SINAD) of 36.7dB
with a 125MHz input tone. The analog input of the
MAX107 is designed for differential or single-ended use
with a ±400mV full-scale input range. In addition, the
MAX107 features an on-board +2.5V precision
bandgap reference, which is scaled to meet the analog
input full-scale range.
Principle of Operation
The MAX107 employs a flash or parallel architecture.
The key to this high-speed flash architecture is the use
of an innovative, high-performance comparator design.
Each quantizer and downstream logic translates the
comparator outputs into 6-bit, parallel codes in two’s
complement format and passes them on to the internal
6:12 demultiplexer. The demultiplexer enables the
ADCs to provide their output data at half the sampling
speed on primary and auxiliary ports. LVDS data is
available at speeds of up to 200MHz per output port.
Input Amplifier Circuits
As with all ADCs, if the input waveform is changing
rapidly during conversion, effective number of bits
(ENOB), signal-to-noise plus distortion (SINAD), and
signal-to-noise ratio (SNR) specifications will degrade.
The MAX107’s on-board, wide-bandwidth input ampli-
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet MAX107.PDF ] | |
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