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PDF MC10E143 Data sheet ( Hoja de datos )
| Número de pieza | MC10E143 | |
| Descripción | 9-BIT HOLD REGISTER | |
| Fabricantes | ON Semiconductor | |
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MC10E143, MC100E143
5 V ECL 9‐Bit Hold Register
Description
The MC10E/100E143 is a 9-bit holding register, designed with
byte-parity applications in mind. The E143 holds current data or loads
new data, with the nine inputs D0 − D8 accepting parallel input data.
The SEL (Select) input pin is used to switch between the two modes
of operation − HOLD and LOAD. Input data is accepted by the
registers a set-up time before the positive going edge of CLK1 or
CLK2. A HIGH on the Master Reset pin (MR) asynchronously resets
all the registers to zero.
The 100 Series contains temperature compensation.
Features
• 700 MHz Min. Operating Frequency
• 9-Bit for Byte-Parity Applications
• Asynchronous Master Reset
• Dual Clocks
• PECL Mode Operating Range:
♦ VCC= 4.2 V to 5.7 V with VEE= 0 V
• NECL Mode Operating Range:
♦ VCC= 0 V with VEE = −4.2 V to −5.7 V
• Internal Input 50 kW Pulldown Resistors
• ESD Protection:
♦ Human Body Model; > 2 kV
♦ Machine Model; > 200 V
• Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level: 3 (Pb-Free)
♦ For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 484 devices
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
www.onsemi.com
PLCC−28
FN SUFFIX
CASE 776−02
MARKING DIAGRAM*
1
MCxxxE143FNG
AWLYYWW
xxx = 10 or 100
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb-Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device
MC10E143FNR2G
MC100E143FNG
Package
PLCC−28
(Pb-Free)
PLCC−28
(Pb-Free)
Shipping†
500/Tape & Reel
37 Units/Tube
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 8
1
Publication Order Number:
MC10E143/D
1 page  
MC10E143, MC100E143
Table 8. AC CHARACTERISTICS (VCCx = 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = −5.0 V (Note 1))
0°C 25°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min
fSHIFT
tPLHt
PHL
Max. Shift Frequency
Propagation Delay To Output
Clk
MR
700 900
700 900
700
600 800 1000 600 800 1000 600
600 800 1000 600 800 1000 600
ts
Setup Time
D
SEL
50 −100
300 150
50 −100
300 150
50
300
th
Hold Time
D
SEL
300 100
75 −150
300 100
75 −150
300
75
tRR Reset Recovery Time
tPW Minimum Pulse Width
Clk, MR
900 700
400
900 700
400
900
400
tSKEW
tJITTER
Tr
tf
Within-Device Skew (Note 2)
Random Clock Jitter (RMS)
Rise/Fall Times
(20 - 80%)
75 75
<1 <1
300 525 800 300 525 800 300
85°C
Typ
900
Max
800 1000
800 1000
−100
150
100
−150
700
75
<1
525 800
Unit
MHz
ps
ps
ps
ps
ps
ps
ps
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. 10 Series: VEE can vary −0.46 V / +0.06 V.
100 Series: VEE can vary −0.46 V / +0.8 V.
2. Within-device skew is defined as identical transitions on similar paths through a device.
Driver
Device
Q
Q
Zo = 50 W
Zo = 50 W
50 W
50 W
D
Receiver
Device
D
VTT
VTT = VCC − 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1405/D − ECL Clock Distribution Techniques
AN1406/D − Designing with PECL (ECL at +5.0 V)
AN1503/D − ECLinPSt I/O SPiCE Modeling Kit
AN1504/D − Metastability and the ECLinPS Family
AN1568/D − Interfacing Between LVDS and ECL
AN1672/D − The ECL Translator Guide
AND8001/D − Odd Number Counters Design
AND8002/D − Marking and Date Codes
AND8020/D − Termination of ECL Logic Devices
AND8066/D − Interfacing with ECLinPS
AND8090/D − AC Characteristics of ECL Devices
www.onsemi.com
5
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| PDF Descargar | [ Datasheet MC10E143.PDF ] | |
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