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PDF LMX2305 Data sheet ( Hoja de datos )
| Número de pieza | LMX2305 | |
| Descripción | PLLatinumTM 550 MHz Frequency Synthesizer for RF Personal Communications | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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PRELIMINARY
August 1996
LMX2305
PLLatinumTM 550 MHz Frequency Synthesizer
for RF Personal Communications
General Description
The LMX2305 is a high performance frequency synthesizer
with an integrated prescaler designed for RF operation up to
550 MHz It is fabricated using National’s ABiC IV BiCMOS
process
The LMX2305 contains a dual modulus prescaler which can
select either a 64 65 or a 128 129 divide ratio at input fre-
quencies of up to 550 MHz LMX2305 which employs the
digital phase lock loop technique combined with a high
quality reference oscillator and a loop filter provides the
tuning voltage for the voltage controlled oscillator to gener-
ate a very stable low noise local oscillator signal
Serial data is transferred into the LMX2305 via a three line
MICROWIRETM interface (Data Enable Clock) Supply volt-
age can range from 2 65V to 5 5V The LMX2305 features
very low current consumption typically 4 0 mA at 2 75V
The LMX2305 is available in a TSSOP 20-pin surface mount
plastic package
Features
Y RF operation up to 550 MHz
Y 2 65V to 5 5V operation
Y Low current consumption
ICC e 4 0 mA (typ) at VCC e 2 75V
Y Dual modulus prescaler 64 65 or 128 129
Y Internal balanced low leakage charge pump
Y Small-outline plastic surface mount TSSOP
0 173 wide package
Applications
Y Analog Cellular telephone systems
(AMPS ETACS NMT)
Y Portable wireless communications
(PCS PCN cordless)
Y Wireless local area networks (WLANs)
Y Other wireless communication systems
Y Pagers
Block Diagram
TL W 12459 – 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
MICROWIRETM and PLLatinumTM are trademarks of National Semiconductor Corporation
C1996 National Semiconductor Corporation TL W 12459
RRD-B30M126 Printed in U S A
http www national com
1 page  
Electrical Characteristics VCC e 2 75V VP e 2 75V b40 C k TA k 85 C except as specified (Continued)
Symbol
Parameter
Conditions
Min Typ Max Units
IDo-source
IDo-sink
IDo-Tri
Charge Pump Output Current
Charge Pump TRI-STATE Current
VDo e VP 2
VDo e VP 2
0 5V s VDo s VP b 0 5V
TA e b40 C k TA k 85 C
10
b5 0
b2 5
25
b1 0
50
mA
mA
nA
VOH
VOL
VOH
VOL
IOL
High-Level Output Voltage
Low-Level Output Voltage
High-Level Output Voltage (OSCOUT)
Low-Level Output Voltage (OSCOUT)
Open Drain Output Current (wp)
IOH e b1 0 mA
IOL e 1 0 mA
IOH e b200 mA
IOL e 200 mA
VOL e 0 4V
VCC b 0 8
VCC b 0 8
10
V
04 V
V
04 V
mA
IOH
Open Drain Output Current (wp)
VOH e 2 75V
100 mA
tCS
tCH
tCWH
tCWL
tES
tEW
Data to Clock Set Up Time
Data to Clock Hold Time
Clock Pulse Width High
Clock Pulse Width Low
Clock to Enable Set Up Time
Enable Pulse Width
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
50
10
50
50
50
50
ns
ns
ns
ns
ns
ns
Except OSCOUT
5 http www national com
5 Page 
Application Information
LOOP FILTER DESIGN
A block diagram of the basic phase locked loop is shown
FIGURE 1 Basic Charge Pump Phase Locked Loop
An example of a passive loop filter configuration including
the transfer function of the loop filter is shown in Figure 2
TL W 12459 – 24
TL W 12459 – 25
s (C2 # R2) a 1
Z(s) e s2 (C1 # C2 # R2) a sC1 a sC2
FIGURE 2 2nd Order Passive Filter
Define the time constants which determine the pole and
zero frequencies of the filter transfer function by letting
T2 e R2 # C2
(1a)
and
T1 e R2 # C1 # C2
C1 a C2
(1b)
The PLL linear model control circuit is shown along with the
open loop transfer function in Figure 3 Using the phase
detector and VCO gain constants Kw and KVCO and the
loop filter transfer function Z(s) the open loop Bode plot
can be calculated The loop bandwidth is shown on the
Bode plot (0p) as the point of unity gain The phase margin
is shown to be the difference between the phase at the unity
gain point and b180
TL W 12459 – 27
Open Loop Gain e ii ie e H(s) G(s)
e Kw Z(s) KVCO Ns
Closed Loop Gain e io ii e G(s) 1 a H(s) G(s)
TL W 12459 – 26
FIGURE 3 Open Loop Transfer Function
Thus we can calculate the 3rd order PLL Open Loop Gain in
terms of frequency
lG(s)
#
H(s)
s
e
j
#
0
e
bKw # KVCO (1 a j0 # T2)
02C1 # N(1 a j0 # T1)
#
T1
T2
(2)
From equation 2 we can see that the phase term will be
dependent on the single pole and zero such that
w(0) e tanb1 (0 # T2) b tanb1 (0 # T1) a 180 (3)
By setting
dw T2
T1
d0 e 1 a (0 # T2)2 b 1 a (0 # T1)2 e 0
(4)
we find the frequency point corresponding to the phase in-
flection point in terms of the filter time constants T1 and T2
This relationship is given in equation 5
0p e 1 0T2 # T1
(5)
For the loop to be stable the unity gain point must occur
before the phase reaches b180 degrees We therefore
want the phase margin to be at a maximum when the magni-
tude of the open loop gain equals 1 Equation 2 then gives
C1
e
Kw # KVCO
0p2 # N #
# T1
T2
(1 a j0p # T2)
(1 a j0p # T1)
(6)
11 http www national com
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| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet LMX2305.PDF ] | |
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