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PDF LMX1601 Data sheet ( Hoja de datos )
| Número de pieza | LMX1601 | |
| Descripción | PLLatinum Low Cost Dual Frequency Synthesizer | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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PRELIMINARY
March 1998
LMX1600/LMX1601/LMX1602
PLLatinum™ Low Cost Dual Frequency Synthesizer
LMX1600
LMX1601
LMX1602
2.0 GHz/500 MHz
1.1 GHz/500 MHz
1.1 GHz/1.1 GHz
General Description
The LMX1600/01/02 is part of a family of monolithic inte-
grated dual frequency synthesizers designed to be used in a
local oscillator subsystem for a radio transceiver. It is fabri-
cated using National’s 0.5u ABiC V silicon BiCMOS process.
The LMX1600/01/02 contains two dual modulus prescalers,
four programmable counters, two phase detectors and two
selectable gain charge pumps necessary to provide the con-
trol voltage for two external loop filters and VCO loops. Digi-
tal filtered lock detects for both PLLs are included. Data is
transferred into the LMX1600/01/02 via a MICROWIRE™
serial interface (Data, Clock, LE).
VCC supply voltage can range from 2.7V to 3.6V. The
LMX1600/01/02 features very low current consumption -
typically 4.0 mA at 3V for LMX1601, 5.0 mA at 3V for
LMX1600 or LMX1602. Powerdown for the PLL is hardware
controlled.
The LMX1600/01/02 is available in a 16 pin TSSOP surface
mount plastic package.
Features
n VCC = 2.7V to 3.6V operation
n Low current consumption:
4 mA @ 3V (typ) for LMX1601
5 mA @ 3V (typ) for LMX1600 or LMX1602
n PLL Powerdown mode: ICC = 1 µA typical
n Dual modulus prescaler:
— 2 GHz/500 MHz option: (Main) 32/33 (Aux) 8/9
— 1.1 GHz/500 MHz option: (Main) 16/17 (Aux) 8/9
— 1.1 GHz/1.1 GHz option: (Main) 16/17 (Aux) 16/17
n Digital Filtered Lock Detects
Applications
n Cordless / Cellular / PCS phones
n Other digital mobile phones
Functional Block Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
MICROWIRE™ and PLLatinum™ are trademarks of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100129
DS100129-1
www.national.com
1 page  
1.0 Functional Description
The basic phase-lock-loop (PLL) configuration consists of a
high-stability crystal reference oscillator, a frequency synthe-
sizer such as the National Semiconductor LMX1600/01/02, a
voltage controlled oscillator (VCO), and a passive loop filter.
The frequency synthesizer includes a phase detector, cur-
rent mode charge pump, as well as programmable reference
[R], and feedback [N] frequency dividers. The VCO fre-
quency is established by dividing the crystal reference signal
down via the R counter to obtain the comparison frequency.
This reference signal, fr, is then presented to the input of a
phase/frequency detector and compared with another signal,
fp, the feedback signal, which was obtained by dividing the
VCO frequency down using the N counter. The phase/
frequency detector’s current source outputs pump charge
into the loop filter, which then converts the charge into the
VCO’s control voltage. The phase/frequency comparator’s
function is to adjust the voltage presented to the VCO until
the feedback signal’s frequency (and phase) match that of
the reference signal. When this “phase-locked” condition ex-
ists, the VCO’s frequency will be N times that of the compari-
son frequency, where N is the divider ratio.
1.1 REFERENCE OSCILLATOR INPUTS
The reference oscillator frequency for the Main and Aux
PLL’s is provided by either an external reference through the
OSCIN pin with the OSCOUT pin not connected or connected
to a 30 pF capacitor to ground in Logic Mode, or an external
crystal resonator across the OSCIN and OSCOUT pins in
Crystal Mode (See Programming Description 2.5.3). The
OSCIN input can operate to 40 MHz in Logic Mode or to 20
MHz in Crystal Mode with an input sensitivity of 0.5 VPP. The
OSCIN pin drives the Main and Aux R counters. The inputs
have a z 1.2V input threshold and can be driven from an ex-
ternal CMOS or TTL logic gate. The OSCIN pin is typically
connected to the output of a Temperature Compensated
Crystal Oscillator (TCXO).
1.2 REFERENCE DIVIDERS (R COUNTERS)
The Main and Aux R Counters are clocked through the oscil-
lator block in common. The maximum frequency is 40 MHz
in Logic Mode or 20 MHz in crystal Mode. Both R Counters
are 12-bit CMOS counters with a divide range from 2 to
4,095. (See Programming Description 2.2)
1.3 FEEDBACK DIVIDERS (N COUNTERS)
The Main and Aux N Counters are clocked by the small sig-
nal fin Main and fin Aux input pins respectively. These inputs
should be AC coupled through external capacitors. The Main
N counter has an 16-bit equivalent integer divisor configured
as a 5-bit A Counter and an 11-bit B Counter offering a con-
tinuous divide range from 992 to 65,535 (2 GHz option) or a
4-bit A Counter and a 12-bit B Counter offering a continuous
divide range from 240 to 65,535 (1.1 GHz option). The Main
N divider incorporates a 32/33 dual modulus prescaler ca-
pable of operation from 200 MHz to 2.0 GHz or a 16/17 dual
modulus prescaler capable of operation from 100 MHz to
1.1 GHz.
The Aux N divider operates from 100 MHz to 1.1 GHz with a
16/17 prescaler or from 40 MHz to 500 MHz with a 8/9 pres-
caler. The Aux N counter is a 16-bit integer divider fully pro-
grammable from 240 to 65,535 over the frequency range of
100 MHz to 1.1 GHz or from 56 to 32,767 over the frequency
range of 40 MHz to 550 MHz. The Aux N counter is config-
ured as a 4-bit A Counter and a 12-bit B Counter. These in-
puts should be AC coupled through external capacitors. (See
Programming Description 2.3)
1.3.1 Prescalers
The RF input to the prescalers consists of the fin pins which
are one of two complimentary inputs to a differential pair am-
plifier. The complimentary inputs are internally coupled to
ground with a 10 pF capacitor and not brought out to a pin.
The input buffer drives the A counter’s ECL D-type flip flops
in a dual modulus configuration. A 32/33 for 2.0 GHz option,
16/17 for 1.1 GHz option, or 8/9 for 500 MHz option prescale
ratio is provided for the LMX1600/01/02. The prescaler
clocks the subsequent CMOS flip-flop chain comprising the
fully programmable A and B counters.
1.4 PHASE/FREQUENCY DETECTOR
The Main and Aux phase(/frequency) detectors are driven
from their respective N and R counter outputs. The maxi-
mum frequency at the phase detector inputs is 10 MHz (un-
less limited by the minimum continuous divide ratio of the
multi modulus prescalers). The phase detector outputs con-
trol the charge pumps. The polarity of the pump-up or pump-
down control is programmed using Main_PD_Pol or
Aux_PD_Pol depending on whether Main or Aux VCO char-
acteristics are positive or negative. (See Programming De-
scription 2.4) The phase detector also receives a feedback
signal from the charge pump in order to eliminate dead zone.
1.5 CHARGE PUMP
The phase detector’s current source outputs pump charge
into an external loop filter, which then converts the charge
into the VCO’s control voltage. The charge pumps steer the
charge pump output, CPo, to VCC (pump-up) or ground
(pump-down). When locked, CPo is primarily in a
TRI-STATE mode with small corrections. The charge pump
output current magnitude can be selected as 160 µA or 1600
µA using bits AUX_CP_GAIN and MAIN_CP_GAIN as
shown in Programming Description 2.4.
1.7 MICROWIRE SERIAL INTERFACE
The programmable functions are accessed through the MI-
CROWIRE serial interface. The interface is made of 3 func-
tions: clock, data, and latch enable (LE). Serial data for the
various counters is clocked in from data on the rising edge of
clock, into the 18-bit shift register. Data is entered MSB first.
The last two bits decode the internal register address. On the
rising edge of LE, data stored in the shift register is loaded
into one of the 4 appropriate latches (selected by address
bits). Data is loaded from the latch to the counter when
counter reaches to zero. A complete programming descrip-
tion is included in the following sections.
1.8 FoLD MULTIFUNCTION OUTPUT
The LMX1600/01/02 programmable output pin (FoLD) can
deliver the internal counter outputs, digital lock detects, or
CMOS high/low levels.
1.8.1 Lock Detect
A digital filtered lock detect function is included with each
phase detector through an internal digital filter to produce a
logic level output available on the Fo/LD output pin, if se-
lected. The lock detect output is high when the error between
5 www.national.com
5 Page 
2.0 Programming Description (Continued)
2.5.1 Lock Detect Digital Filter
The Lock Detect Digital Filter compares the difference between the phase of the inputs of the phase detector to a RC generated
delay of approximately 15 ns. To enter the locked state (Lock = HIGH) the phase error must be less than the 15 ns RC delay for
4 consecutive reference cycles. Once in lock (Lock = HIGH), the RC delay is changed to approximately 30 ns. To exit the locked
state (Lock = LOW), the phase error must become greater than the 30 ns RC delay. When the PLL is in the powerdown mode,
Lock is forced LOW. A flow chart of the digital filter is shown below.
2.5.2 Typical Lock Detect Timing (AUX_PD_POL/MAIN_PD_POL = 1)
DS100129-16
DS100129-17
11 www.national.com
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet LMX1601.PDF ] | |
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