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PDF LM9637 Data sheet ( Hoja de datos )
| Número de pieza | LM9637 | |
| Descripción | LM9637 Monochrome CMOS Image Sensor VGA 68 FPS | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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ADVANCE INFORMATION
MAY 2002
LM9637 Monochrome CMOS Image Sensor VGA 68 FPS
General Description
The LM9637 is a high performance, low power, 1/4" VGA CMOS
Active Pixel Sensor capable of capturing monochrome still or
motion images and converting them to a digital data stream.
Excellent image quality is achieved by integrating a high perfor-
mance analog signal processor comprising of a high speed 10
bit A/D convertor, fixed pattern noise elimination circuits and a
programmable gain amplifier. The offset and black level can be
automatically adjusted on chip using a full loop black level com-
pensation circuit.
Furthermore, a programmable smart timing and control circuit
allowing the user maximum flexibility in adjusting integration
time, active window size, gain, frame rate. Various control, tim-
ing and power modes are also provided.
Features
f Master and slave mode operation
f Progressive scan read out with horizontal and vertical flip
f Programmable Exposure:
- Master clock divider
- Inter row delay
- Inter frame delay
- Partial frame integration
f Programmable gain amplifier
f Full automatic servo loop for black level & offset adjustment
on each gain channel
f Horizontal & vertical sub-sampling (2:1 & 4:2) with averaging
f Windowing
f Programmable pixel clock, inter-frame and inter-line delays
f I2C compatible serial control interface
f Power on reset & power down mode
Applications
f Security Camera
f Machine Vision
f Barcode Scanners
f Biometrics
Key Specifications
Array Format
Effective Image Area
Optical Format
Pixel Size
Video Outputs
Frame Rate
Dynamic Range
Electronic Shutter
FPN
PRMU
Sensitivity
Fill Factor
Micro Lens
Package
Single Supply
Power Consumption
Operating Temp
Total: 488 x 672
Active: 488 x 648
Total: 2.93mm x 4.03mm
Active: 2.93mm x 3.89mm
1/4"
6.0µm x 6.0µm
8 & 10 Bit Digital
68 frames per second
57 dB
Rolling Reset
0.5%
1.7%
2.40 volts/lux.s
49%
none
32 LCC
3.0V +/-10%
130mW
-10oC to 50 oC
Overall Chip Block Diagram
sclk sda sadr resetb
pwd
mclk
APS Array
Register
Bank
I2C Compatible
Serial I/F
POR
Power
Control
clk gen
Master Sensor Controller
snapshot
extsync
Column CDS
+/- Amp
10 bit A/D
Figure 1. Chip Block Diagram
©2002 National Semiconductor Corporation
d[9:0]
pclk
hsync
vsync
www.national.com
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