|
|
PDF 74LS161 Data sheet ( Hoja de datos )
| Número de pieza | 74LS161 | |
| Descripción | Synchronous 4 Bit Counters; Binary/ Direct Reset | |
| Fabricantes | System Logic Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de 74LS161 (archivo pdf) en la parte inferior de esta página. Total 5 Páginas | ||
|
No Preview Available !
SL74LS161
Synchronous 4 Bit Counters; Binary,
Direct Reset
This synchronous, presettable counter features an internal carry
look-ahead for application in high-speed counting designs.
Synchronous operation is provided by having all flip-flops clocked
simultaneously so that the outputs change conicident with each other
when so instructed by the count-enable inputs and internal gating.
This mode of operation eliminates the output counting spikes that
are normally associated with asynchronous (ripple clock) counters. A
buffered clock input triggers the four flip-flops on the rising (positive-
going) edge of the clock input wave form.
This counter is fully programmable; that is the outputs may be
preset to either level. As presetting is synchronous setting up a low
level at the load input disables the counter and causes the outputs to
agree with the setup data after the next clock pulse regardless of the
levels of the enable inputs.
The carry look-ahead circuitry provides for cascading counters for
n-bit synchronous applications without additional gating. Instrumental
in accomplishiing this function are two counter-enable inputs and a
ripple carry output. Both countenable inputs (ENABLE P and
ENABLE T) must be high to count, and ENABLE T is fed forward to
enable the ripple carry output. The ripple carry output thus enabled
will produce a high-level output pulse with a duration approximately
equal to the high level portion of the QA output. The high-level
overflow ripple carry pulse can be enable successive cascaded
stages. Transitions at the ENPor ENT are allowed regardless of the
level of the clock input.
• Internal Look-Ahead for Fast Counting
• Carry Output for n-Bit Cascading
• Synchronous Counting
• Synchronously Programmable
• Load Control Line
• Diode-Clamped Inputs
ORDERING INFORMATION
SL74LS161N Plastic
SL74LS161D SOIC
TA = 0° to 70° C for all
packages
PIN ASSIGNMENT
LOGIC DIAGRAM
SLS
System Logic
Semiconductor
PIN 16 =VCC
PIN 8 = GND
1 page  
SL74LS161
NOTES A. CL includes probe and jig capacitance.
B. All diodes are 1N916 or 1N3064.
Figure 5. Test Circuit
Sequence illustrated in waveforms:
1. Reset outputs to zero.
2. Preset to binary twelve.
3. Count to thirteen, fourteen, fifteen, zero, one, and two.
4. Inhibit.
Figure 7. Timing Diagram
SLS
System Logic
Semiconductor
5 Page | ||
| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet 74LS161.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| 74LS16 | HEX INVERTER BUFFERS/DRIVERS |  Texas Instruments |
| 74LS160 | BCD DECADE COUNTERS / 4-BIT BINARY COUNTERS |  SYC |
| 74LS160 | BCD DECADE COUNTERS/ 4-BIT BINARY COUNTERS |  ON Semiconductor |
| 74LS160 | Synchronous Decade Counters(direct clear) |  Hitachi Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |