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PDF SMP9212 Data sheet ( Hoja de datos )
| Número de pieza | SMP9212 | |
| Descripción | Dual 10-bit Nonvolatile DAC | |
| Fabricantes | ETC | |
| Logotipo |  |
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SUMMIT
MICROELECTRONICS, Inc.
SMP9210 SMP9211 SMP9212
Dual 10-bit Nonvolatile DAC
In-system Programmable Analog
FEATURES
• Two 10-bit Nonvolatile DACs
− INL ± 1LSB
− DNL: ± 1LSB
ISPa™
• Programmable Configuration
• Programmable Power-on Reset Options
− Recall Full Scale Value
− Recall Zero Scale Value
− Recall Mid-Scale Value
− Recall NV Register Value
• Tandem or Independent Operation of DACs
• Power-down mode (short VOUT to gnd)
OVERVIEW
The SMP9210 is a serial input, voltage output, dual
10-bit digital to analog converter. It can operate from
a single +2.7V to +5.5V supply. Internal precision
buffers swing rail-to-rail with an input reference range
from ground to the positive supply.
The SMP9210 integrates two 10-bit DACs and their
associated circuits that include; an enhanced unity
gain operational amplifier output, a 10-bit volatile data
latch, a 10-bit nonvolatile data register and an
industry standard 2-wire serial interface.
BLOCK DIAGRAM
Advance Information
page 1 of 1
1 page  
SUMMIT
MICROELECTRONICS, Inc.
SMP9210 SMP9211 SMP9212
Table 1. Command Structure.
MSB
LSB
76543210
Command
Function
1 0 0 1 dc dc D9 D8
Write DAC1
Write 10-bit value to DAC1
1 0 1 0 dc dc D9 D8
Write DAC2
Write 10-bit value to DAC2
1
0
1
1
dc
dc
D9
D8
Write Both DACS
Write the same 10-bit value to DAC1
and DAC2
11011110
ZeroDAC1
Set DAC1 to Zero Scale (VREFL)
11011101
ZeroDAC2
Set DAC2 to Zero Scale (VREFL)
11011111
ZeroBOTH
Set DAC1 & DAC2 to Zero Scale (VREFL)
11101110
3FDAC1
Set DAC1 to Full Scale (VREFL)
11101101
3FDAC2
Set DAC2 to Full Scale (VREFL)
11101111
1 1 1 1 dc dc 1 0
1 1 1 1 dc dc 0 1
1 1 1 1 dc dc 1 1
3FBOTH
RecallDAC1
RecallDAC2
RecallBoth
Set DAC1 & DAC2 to Full Scale (VREFL)
Recall E2 to DAC1
Recall E2 to DAC2
Recall E2 to Both DACs
1 0 0 0 dc dc 1 0
PDDAC1
Power Down DAC1 (VOUT to GND)
1 0 0 0 dc dc 0 1
PDDAC2
Power Down DAC2 (VOUT to GND)
10
*dc = don't care
0
0 dc dc 1
1
PDBOTH
Power Down Both DACs (VOUT to GND)
type/address byte followed by the command byte.
They are will be enforced with or without a stop being
issued and the new register value is never stored in
the nonvolatile register.
Writing a value to a DAC can either be a write to the
DAC register only or a combined write to both the
DAC Register and its nonvolatile register. They are
identical with the one exception being the register
write does not entail issuing a stop condition;
whereas, the nonvolatile write operation is concluded
with a stop.
The sequence is to issue a start, followed by the
device type and bus address, with the read/write bit
set to zero. The SMP9210 will respond with an
acknowledge and the master will then issue the
command and follow-on data. In the example below
the write is to DAC1, where the command = 1001[b];
the dc bits are don't care, D9 and D8 are the MSBs of
the DAC value being written. The SMP9210 will then
respond with an acknowledge followed by the master
writing the last eight bits. In the first example shown,
no stop is generated after the SMP9210
acknowledge; therefore, the write is only to the
register. In the second example the SMP9210
acknowledge is followed by a stop; therefore, the
data is written to both the DAC register and to the
nonvolatile register.
Writing to DACs Data Sequence (Volatile Write)
S
t
a
0
r
1
0
1
A
2
A
1
A
0
0
A
C
K
1
00
1
d
c
d
c
D
9
D
8
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
t Device Type and Bus Address W
Command
Writing to DACs Data Sequence (Nonvolatile Write)
S
t
a
0
r
t
1
0
1
AAA
210
0
A
C
1
K
0
0
1
d
c
d
c
D
9
D
8
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
S
t
o
p
Command Sequence (example command shown 3FDAC1)
S
t
a
0
1
0
1
A
2
A
1
A
0
0
A
C
1
11
011
1
0
A
C
r KK
t Device Type and Bus Address W
Command
Advance Information
page 5 of 5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet SMP9212.PDF ] | |
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