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PDF TSEV8388BF Data sheet ( Hoja de datos )

Número de pieza TSEV8388BF
Descripción ADC 8-bit 1 GSPS
Fabricantes ATMEL Corporation 
Logotipo ATMEL Corporation Logotipo



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Features
8-bit Resolution
ADC Gain Adjust
1.5 GHz Full Power Input Bandwidth (-3 dB)
1 GSPS (min) Sampling Rate
SINAD = 44.3 dB (7.2 Effective Bits), SFDR = 58 dBc,
at FS = 1 GSPS, FIN = 20 MHz
SINAD = 42.9 dB (7.0 Effective Bits), SFDR = 52 dBc,
at FS = 1 GSPS, FIN = 500 MHz
SINAD = 40.3 dB (6.8 Effective Bits), SFDR = 50 dBc,
at FS = 1 GSPS, FIN = 1000 MHz (-3 dB FS)
2-tone IMD: -52 dBc (489 MHz, 490 MHz) at 1 GSPS
DNL = 0.3 lsb, INL = 0.7 lsb
Low Bit Error Rate (10-13) at 1 GSPS
Very Low Input Capacitance: 3 pF
500 mVpp Differential or Single-ended Analog Inputs
Differential or Single-ended 50ECL Compatible Clock Inputs
ECL or LVDS/HSTL Output Compatibility
Data Ready Output with Asynchronous Reset
Gray or Binary Selectable Output Data; NRZ Output Mode
Power Consumption: 3.4W at Tj = 70°C Typical
Radiation Tolerance Oriented Design (150 Krad (Si) measured)
Two Package Versions
Evaluation board: TSEV8388B
Demultiplexer TS81102G0: Companion Device Available
ADC 8-bit
1 GSPS
TS8388B
Applications
• Digital Sampling Oscilloscopes
• Satellite Receiver
• Electronic Countermeasures/Electronic Warfare
• Direct RF Down-conversion
Description
The TS8388B is a monolithic 8-bit analog-to-digital converter, designed for digitizing
wide bandwidth analog signals at very high sampling rates of up to 1 GSPS.
The TS8388B uses an innovative architecture,
including an on-chip Sample and Hold (S/H),
and is fabricated with an advanced
high speed bipolar process.
The on-chip S/H has a 1.5 GHz full power
input bandwidth, providing excellent dynamic
performance in undersampling applications
(High IF digitizing).
Rev. 2144C–BDC–04/03
1

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TSEV8388BF pdf
TS8388B
Table 3. Electrical Specifications (Continued)
Parameter
Positive supply current
Analog
Digital
Negative supply voltage
Negative supply current
Analog
Digital
Nominal power dissipation
Power supply rejection ratio
Resolution
Analog Inputs
Full Scale Input Voltage range (differential mode)
(0V common mode voltage)
Full Scale Input Voltage range (single-ended input
option) (See Application Notes)
Analog input capacitance
Input bias current
Input Resistance
Full Power input Bandwidth (-3dB)
CBGA68 package
CQFP68 package
Small signal input Bandwidth (10% full scale)
Clock Inputs
Logic compatibility for clock inputs
(See Application Notes)
ECL Clock inputs voltages (VCLK or VCLKB):
Logic “0” voltage
Logic “1” voltage
Logic “0” current
Logic “1” current
Clock input power level into 50termination
Clock input power level
Clock input capacitance
Symbol
ICC
IPLUSD
VEE
AIEE
DIEE
PD
PSRR
VIN
VINB
VIN
VINB
CIN
IIN
RIN
FPBW
SSBW
VIL
VIH
IIL
IIH
CCLK
Test
Level
Min
1, 2
6
1, 2
6
1, 2, 6
-5.3
1, 2 –
6–
1, 2 –
6–
1, 2 –
6–
4–
––
Value
Typ
385
395
115
120
-5
165
170
135
145
3.4
3.6
0.5
8
Max
445
445
145
145
-4.7
200
200
180
180
4.1
4.3
2
4 -125 – 125
– -125 – 125
4 -250 – 250
–– 0 –
4–
3 3.5
4–
10 20
4 0.5
1
–– – –
4 – 1.8 –
4 – 1.5 –
4 1.5 1.7
ECL or specified clock input
power level in dBm
4– – –
––
– -1.5
– -1.1
––
5 50
––
5 50
– dBm into 50
4 -2 4 10
4–
3 3.5
Unit Note
mA
mA
mA
mA
V
mA
mA
mA
mA
W
W
mW
bits (2)
mV
mV
mV
mV
pF
µA
M
GHz
GHz
GHz
V
V
µA
µA
dBm
pF
(10)
2144C–BDC–04/03
5

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TSEV8388BF arduino
TS8388B
Explanation of
Test Levels
Table 4. Explanation of Test Levels
Num
1
2
Characteristics
100% production tested at +25°C(1) (for “C” Temperature range(2)).
100% production tested at +25°C(1), and sample tested at specified temperatures
(for “V” and “M” Temperature range(2)).
3 Sample tested only at specified temperatures.
4
Parameter is guaranteed by design and characterization testing (thermal steady-state
conditions at specified temperature).
5 Parameter is a typical value only.
6
100% production tested over specified temperature range
(for “B/Q” Temperature range(2)).
Notes:
1. Unless otherwise specified, all tests are pulsed tests: therefore Tj = Tc = Ta, where Tj, Tc
and Ta are junction, case and ambient temperature respectively.
2. Refer to “Ordering Information” on page 50.
3. Only MIN and MAX values are guaranteed (typical values are issuing from characterization
results).
Functions
Description
Table 5. Functions Description
Name
Function
VCC
VEE
VPLUSD
GND
Positive power supply
Analog negative power supply
Digital positive power supply
Ground
VIN, VINB
CLK, CLKB
Differential analog inputs
Differential clock inputs
<D0:D7>
<D0B:D7B>
Differential output data port
DR, DRB
Differential data ready outputs
OR, ORB
Out of range outputs
GAIN
ADC gain adjust
GORB
Gray or Binary digital output select
DIOD/DRRB
Die junction temperature measurement/
asynchronous data ready reset
VCC = +5V
VPLUSD = +0V (ECL)
VPLUSD = +2.4V (LVDS)
VIN
VINB
CLK
CLKB
GAIN
GORG
DIOD/
DRRB
TS8388B
OR
ORB
D0
16 D0B
DR
DRB
D7
D7B
DVEE = -5V VEE = -5V GND
2144C–BDC–04/03
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