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Número de pieza TSEV8308500GLZA2
Descripción ADC 8-bit 500 Msps
Fabricantes ATMEL Corporation 
Logotipo ATMEL Corporation Logotipo



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Main Features
8-bit Resolution
500 Msps (min) Sampling Rate
Power Consumption: 3.8W Typ
500 mVpp Differential or Single-ended Analog Inputs
Differential or Single-ended 50ECL Compatible Clock Inputs
ECL or LVDS/HSTL Output Compatibility
ADC Gain Adjust
Data Ready Output with Asynchronous Reset
Gray or Binary Selectable Output Data; NRZ Output Mode
Enhanced CBGA Package with Ceramic Lid
Evaluation Board: TSEV8308500GL (Detailed Specification on Request)
Demultiplexer TS81102G0: Companion Device Available
Performance
1.3 GHz Full Power Input Bandwidth
Band Flatness: 0.5 dB up to 500 MHz
SINAD = 45 dB (7.2 Effective Bits), SFDR = 54 dBc
at FS = 500 Msps, FIN = 20 MHz
SINAD = 43 dB (7.1 Effective Bits), SFDR = 53 dBc
at FS = 500 Msps, FIN = 250 MHz
SINAD = 42 dB (7.0 Effective Bits), SFDR = 52 dBc
at FS = 500 Msps, FIN = 500 MHz (-3 dB FS)
2-tone IMD: TBD (199.5 MHz, 200.5 MHz) at 500 Msps
DNL = ±0.3 LSB INL = ±0.7 LSB
Low Bit Error Rate (10-13) at 500 Msps, Tj = 90°C
ADC 8-bit
500 Msps
TS8308500
Applications
• Digital Sampling Oscilloscopes
• Satellite Receiver
• Electronic Countermeasures/Electronic Warfare
• Direct RF Down-conversion
Screening
• Atmel Standard Screening Level
• Temperature Range:
– 0°C < Tc; Tj < +90°C
– -40°C < Tc ; Tj < + 110°C
Description
The TS8308500 is a monolithic 8-bit analog-to-digital converter, designed for digitizing
wide bandwidth analog signals at very high sampling rates of up to 500 Msps.
The TS8308500 is using an innovative architecture, including an on-chip Sample and
Hold (S/H), and is fabricated with an advanced high-speed bipolar process.
The on-chip S/H has a 1.3 GHz full power input bandwidth, providing excellent
dynamic performance in undersampling applications (High IF digitizing).
Rev. 2193A–BDC–046/03
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TSEV8308500GLZA2 pdf
TS8308500
Table 3. Electrical Specifications (Continued)
Parameter
Symbol
Test
Level
Min
Value
Typ
Max
Unit
Clock input power level
– 4 -2 4 10 dBm
Clock input capacitance
CCLK
4
3
Digital Outputs
Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), binary output data format,
Tj (typical) = 70°C. Full temperature range: 0°C < Tc; Tj < +90°C or -40°C < Tc ; Tj < 110°C
3.5
pF
Logic compatibility for digital outputs
(Depending on the value of VPLUSD) (14)
Differential output voltage swings
(assuming VPLUSD = 0V):
75open transmission lines (ECL levels)
––
ECL or LVDS
– 4– – – –
– 1.5 1.620 –
V
75differentially terminated
– 0.70 0.825 –
V
50differentially terminated
– 0.54 0.660 –
V
Output levels (assuming VPLUSD = 0V)
75open transmission lines:
– 4– – – –
Logic 0 voltage
Logic 1 voltage
Output levels (assuming VPLUSD = 0V)
75differentially terminated:
VOL
-1.62
-1.54
V
VOH – -0.88 -0.8 –
V
– 4– – – –
Logic 0 voltage
Logic 1 voltage
Output levels (assuming VPLUSD = 0V)
50differentially terminated:
VOL
-1.41
-1.34
V
VOH
– -1.07
-1
V
– –– – – –
Logic 0 voltage
Logic 1 voltage
Differential Output Swing
VOL
VOH
DOS
1, 2
-1.40
-1.32
1, 2 -1.16 -1.10
4 270 300
V
V
mV
Output level drift with temperature
– 4 – – 1.6 mV/°C
DC Accuracy
Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format
Tj (typical) = 70°C
Differential non linearity
DNL-
1 -0.6 -0.4
– lsb/V
Differential non linearity
DNL+
1
0.4 0.6 lsb/V
Integral non linearity
INL- 1 -1.2 -0.7 – lsb/V
Integral non linearity
INL+
1
0.7 1.2 lsb/V
No missing codes
– Guaranteed over specified temperature range
Gain
– 1, 2 90 98 110 %/V
Input offset voltage
1, 2 -26
-5
26 mV/V
Note
(1)(6)
(6)
(6)
(6)
(2)(3)
(2)(3)
(3)
2193A–BDC–04/03
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TSEV8308500GLZA2 arduino
TS8308500
Digital Output
Coding
NRZ (Non Return to Zero) mode, ideal coding: does not include gain, offset, and linearity volt-
age errors.
Table 6. Digital Output Coding
Differential
Analog Input
> +251 mV
+251 mV
+249 mV
+126 mV
+124 mV
+1 mV
-1 mV
-124 mV
-126 mV
-249 mV
-251 mV
< -251 mV
Voltage Level
> Positive full-scale + 1/2 LSB
Positive full-scale + 1/2 LSB
Positive full-scale - 1/2 LSB
Positive 1/2 scale + 1/2 LSB
Positive 1/2 scale - 1/2 LSB
Bipolar zero + 1/2 LSB
Bipolar zero - 1/2 LSB
Negative 1/2 scale + 1/2 LSB
Negative 1/2 scale - 1/2 LSB
Negative full-scale + 1/2 LSB
Negative full-scale - 1/2 LSB
< Negative full-scale - 1/2
LSB
Digital Output
Binary
GORB = VCC or Floating
Gray
GORB = GND
11111111
10000000
11111111
11111110
10000000
10000001
11000000
10111111
10100000
11100000
10000000
01111111
11000000
01000000
01000000
00111111
01100000
00100000
00000001
00000000
00000001
00000000
00000000
00000000
Out of
Range
1
0
0
0
0
0
0
0
0
0
0
1
2193A–BDC–04/03
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