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PDF SM5165 Data sheet ( Hoja de datos )

Número de pieza SM5165
Descripción PLL Synthesizer IC
Fabricantes Nippon Precision Circuits Inc 
Logotipo Nippon Precision Circuits Inc Logotipo



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NIPPON PRECISION CIRCUITS INC.
SM5165AV
PLL Synthesizer IC
OVERVIEW
The SM5165AV is a PLL synthesizer IC developed
for application in pagers and fabricated using NPC’s
Molybdenum-gate CMOS process. It incorporates
independently-controlled reference frequency and
operating frequency dividers, and operates from a
low-voltage supply to realize low power dissipation.
FEATURES
s Up to 90 MHz operating frequency
(VDD1 = VDD2 = 0.95 V)
s Up to 100 MHz operating frequency
(VDD1 = VDD2 = 1.00 V)
s Supply voltages
• VDD1 = VDD2 = 0.95 to 1.5 V
(prescaler, counters)
• VDD3 = 2.0 to 3.3 V (charge pump)
s 40 to 16376 reference frequency divider ratio
range (with 1/8 prescaler built-in)
s 1056 to 262143 operating frequency divider ratio
range
s Power-save function for reduced power
dissipation
s 10 to 60 °C operating temperature range
s 16-pin VSOP
s Molybdenum-gate CMOS process
APPLICATIONS
s Pagers
ORDERING INFOMATION
Device
SM5165AV
Package
16pin VSOP
PINOUT(TOP VIEW)
16pin VSOP
VDD1
FIN
VSS
RO
TEST
DO
DB
NC
1
8
16 XIN
XOUT
LE
CLK
DATA
OPR
VDD2
9 VDD3
PACKAGE DIMENSIONS
Unit: mm
16-pin VSOP
5.1 0.2
0.22+-
0.10
0.05
0.65
+
0.15 -
00..1005
0 10
0.5 0.2
NIPPON PRECISION CIRCUITS—1

1 page




SM5165 pdf
SM5165AV
FUNCTIONAL DESCRIPTION
Operating Frequency Divider
(N-counter) Structure
The operating frequency divider generates a compar-
ator frequency signal (FV), which is input to the
phase comparator, by dividing the VCO signal input
on pin FIN.
The operating frequency divider is comprised by
dual modulus prescalers, a 5-bit swallow counter and
a 13-bit main counter.
The settings for the dual modulus prescaler (P and P
+ 1), swallow counter (S) and main counter (M) are
related to the comparator frequency divider ratio by:
N = (P + 1) × S + P(M – S)
= PM + S
The counter value ranges are P = 32, P + 1 = 33, S =
0 to 31, and M = 32 to 8191. Therefore, the compara-
tor frequency divider ratio range N is 1056 to
262143.
Reference Frequency Divider
(R-counter) Structure
The reference frequency divider generates a compar-
ator frequency signal (FR), which is input to the
phase comparator, by dividing the reference oscilla-
tor frequency input either from an external signal on
XIN or from a crystal oscillator connected between
XIN and XOUT.
The reference frequency divider is comprised by a
fixed divide-by-8 prescaler and an 11-bit reference
counter.
The settings for the prescaler (A = 8) and reference
counter (R) are related to the reference frequency
divider ratio by:
R = AB = 8B
The counter value ranges are A = 8 and B = 5 to
2047. Therefore, the reference frequency divider
ratio range is R = 40 to 16376.
Input Data
The input data should be specified keeping in mind
both the VDD2 and VDD3 supplies. The data is input
using CLK, DATA and LE pins into the shift register
and latch which operate from the VDD2 supply. How-
ever, the input voltages can be specified using either
the VDD2 or VDD3 supply levels.
The control data input uses a 3-line 23-bit serial
interface comprising the clock (CLK), data input
(DATA) and latch enable (LE). The data is input with
the MSB first. The last (23rd) bit is used as the latch
select control bit. Data is written to the shift register
on the rising edge of the clock signal. Accordingly,
the data should change state on the falling edge of
the clock signal. Data is transferred from the shift
register to the latch when the latch enable (LE) sig-
nal goes HIGH. Accordingly, the latch enable signal
should be held LOW while data is being written to
the shift register.
The clock and data input signals are both ignored
when the latch enable signal goes HIGH.
Input data format
CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
DATA MSB
LSB
CONTROL
LE
NIPPON PRECISION CIRCUITS—5

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