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PDF ISL6528 Data sheet ( Hoja de datos )
| Número de pieza | ISL6528 | |
| Descripción | Dual Regulator - Standard Buck PWM and Linear Power Controller | |
| Fabricantes | Intersil Corporation | |
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TM
Data Sheet
Dual Regulator - Standard Buck PWM
and Linear Power Controller
The ISL6528 provides the power control and protection for
two output voltages in high-performance graphics cards and
other embedded processor applications. The dual-output
controller drives an N-Channel MOSFET in a standard buck
topology and a NPN pass transistor in a linear configuration.
The ISL6528 provides both a regulated high current, low
voltage supply and an independent, lower current supply
integrated in an 8-lead SOIC package. The controller is ideal
for graphics card applications where both graphics
processing unit (GPU) and memory supplies are required.
The standard buck converter is a simple, single feedback
loop, voltage-mode control with fast transient response. Both
the switching regulator and linear regulator provide a
maximum static regulation tolerance of ±2% over line, load,
and temperature ranges. Each output is user-adjustable by
means of external resistors.
An integrated soft-start feature brings both supplies into
regulation in a controlled manner. Each output is monitored
via the FB pins for undervoltage events. If either output
drops below 52.5% of the internal reference voltage, both
regulators are shutdown.
Ordering Information
PART NUMBER TEMP. RANGE (oC) PACKAGE
PKG.
NO.
ISL6528CB
0 to 70
8 Ld SOIC M8.15
ISL6528CB-T
8Ld SOIC Tape and Reel
ISL6528EVAL1 Evaluation Board
Applications
• Graphics–GPU and memory supplies
• ASIC power supplies
• Embedded processor and I/O supplies
• DSP supplies
February 2002
ISL6528
FN9038.1
Features
• Provides two regulated voltages
- One standard buck PWM
- One linear controller
• Small converter size
- 600kHz constant frequency operation
- Small external component count
• Excellent output voltage regulation
- Both outputs: ±2% over temperature
• Single 5V bias and bootstrap supply
• Output voltage range: 0.8V to 3.3V
• Simple single-loop voltage-mode PWM control design
• Fast PWM converter transient response
- High-bandwidth error amplifier
- Full 0–100% duty ratio
• Linear controller drives bipolar linear pass transistor
• Fully-adjustable outputs
• Undervoltage fault monitoring on both outputs
Related Literature
• Technical Brief TB363 Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)
Pinout
TOP VIEW
GND 1
VCC 2
DRIVE2 3
FB2 4
ISL6528
(SOIC)
8 UGATE
7 BOOT
6 COMP
5 FB
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002, All Rights Reserved
1 page  
ISL6528
Functional Pin Descriptions
GND 1
VCC 2
DRIVE2 3
FB2 4
8 UGATE
7 BOOT
6 COMP
5 FB
GND (Pin 1)
Signal ground for the IC. All voltage levels are measured
with respect to this pin. Place via close to pin to minimize
impedance path to ground plane.
VCC (Pin 2)
Provide a well decoupled 5V bias supply for the IC to this
pin. The voltage at this pin is monitored for Power-On Reset
(POR) purposes.
DRIVE2 (Pin 3)
Connect this pin to the base terminal of an external bipolar
NPN transistor. This pin provides the base current drive for
the linear regulator pass transistor.
FB2 (Pin 4)
Connect the output of the linear regulator to this pin through
a properly sized resistor divider. The voltage at this pin is
regulated to 0.8V. This pin is also monitored for undervoltage
events.
Pulling and holding FB2 above 1.25V shuts down both
regulators. Releasing FB2 initiates soft-start on both
regulators.
FB (Pin 5) and COMP (Pin 6)
FB and COMP are the available external pins of the error
amplifier. The FB pin is the inverting input of the error amplifier
and the COMP pin is the error amplifier output. These pins are
used to compensate the voltage-mode control feedback loop of
the standard buck converter.
BOOT (Pin 7)
Connect a suitable capacitor (0.47µF recommended) from
this pin to the source terminal of the upper MOSFET
(PHASE node). This bootstrap capacitor supplies the
UGATE driver the energy necessary to turn and hold the
upper MOSFET on. The absolute maximum voltage on
BOOT must be kept below 10V. This can be met with a 5V
VCC and 3.3V drain supply to the upper MOSFET.
UGATE (Pin 8)
Connect UGATE to the upper MOSFET gate. This pin
provides the gate drive for the MOSFET.
Description
Operation Overview
The ISL6528 monitors and precisely controls two output
voltage levels. Refer to the Block Diagram, Simplified
Power System Diagram, and Typical Application Schematic
on pp. 2–3. The controller is intended for use in graphics
card or embedded processor applications with 3.3V and 5V
bias input available. The IC integrates both a standard buck
PWM controller and a linear controller. The PWM controller
is designed to regulate the high current GPU voltage
(VOUT1). The PWM controller drives a single N-Channel
MOSFET (Q1) in a standard buck converter configuration
and regulates the output voltage to a level programmed by
a resistor divider. The linear controller is designed to
regulate the lower current local memory voltage (VOUT2)
through an external NPN pass transistor.
Initialization
The ISL6528 automatically initializes upon application of
input power. Special sequencing of the input supplies is not
necessary. The POR function continually monitors the input
bias supply voltage at the VCC pin. The POR function
initiates soft-start operation after the 5V bias supply voltage
exceeds its POR threshold.
Soft-Start
The POR function initiates the digital soft-start sequence.
Both the linear regulator error amplifier and PWM error
amplifier reference inputs are forced to track a voltage level
proportional to the soft-start voltage. As the soft-start voltage
slews up, the PWM comparator regulates the output relative
to the tracked soft-start voltage slowly charging the output
capacitor(s). Simultaneously, the linear output follows the
smooth ramp of the soft-start function into normal regulation.
Figure 1 shows the soft-start sequence for a typical application.
At T0, the +5V VCC bias voltage starts to ramp followed by the
3.3V input supply. Once the voltage on VCC crosses the 4.4V
POR threshold at time T1, both outputs begin their soft-start
sequence. The triangle waveform from the PWM oscillator is
compared to the rising error amplifier output voltage. As the
error amplifier voltage increases, the pulse-width on the
UGATE pin increases to reach its steady-state duty cycle at
time T2. The error amplifier reference of the linear controller
also rises relative to the soft-start reference. The resulting soft
ramp on DRIVE2 brings VOUT2 within regulation limits by time
T2.
Undervoltage Protection
The FB and FB2 pins are monitored during converter
operation by two separate undervoltage (UV) comparators. If
the FB voltage drops below 52.5% of the reference voltage
(0.42V), a fault signal is generated. The internal fault logic
5
5 Page 
ISL6528
load current when the base is fed with the minimum driver
output current.
The main criteria for selection of the linear regulator pass
transistor is package selection for efficient removal of heat.
Select a package and heatsink that maintains the junction
temperature below the rating with a maximum expected
ambient temperature.
The power dissipated in a linear regulator is:
PLINEAR ≅ IO × (VIN – VOUT)
(EQ. 17)
where IO is the maximum output current and VOUT is the
nominal output voltage of the linear regulator.
Diode Selection (D1)
Rectifier D1 conducts when MOSFET Q1 is off. The diode
should be a Schottky type for low power losses. The power
dissipation in the Schottky rectifier is approximated by:
PCONDUCTION ≅ IO × Vf × (1 – D)
(EQ. 18)
where IO is the maximum output current of the PWM
converter, Vf is the Schottky forward voltage drop, and D is
the duty cycle of the converter (defined as VO/VIN).
In addition to power dissipation, package selection and
heatsink requirements are the main design trade-offs in
choosing a Schottky rectifier. Since the three factors are
interrelated, the selection process is an iterative procedure.
The maximum junction temperature of the rectifier must
remain below the manufacturer’s specified value, typically
125˚C. By using the package thermal resistance
specification and the Schottky power dissipation equation,
the junction temperature of the rectifier can be estimated. Be
sure to use the available airflow and ambient temperature to
determine the junction temperature rise.
Bootstrap Component Selection
External bootstrap components, a diode and capacitor, are
required to provide sufficient gate enhancement to the
MOSFET. The internal MOSFET gate driver is supplied by
the external bootstrap circuitry as shown in Figure 8. The
boot capacitor, CBOOT, develops a floating supply voltage
referenced to the PHASE pin. This supply is refreshed each
cycle, when D1 conducts, to a voltage of VCC less the boot
diode drop, VD2, plus the voltage rise across D1.
Just after the PWM switching cycle begins and the charge
transfer from the bootstrap capacitor to the gate capacitance
is complete, the voltage on the bootstrap capacitor is at its
lowest point during the switching cycle. The charge lost on
the bootstrap capacitor will be equal to the charge
transferred to the equivalent gate-source capacitance of the
MOSFET as shown in Equation 19.
QGATE = CBOOT × (VBOOT1 – VBOOT2)
(EQ. 19)
+5V
D2
VCC BOOT
+3.3V
CBOOT
ISL6528
UGATE
PHASE
Q1
D1
FIGURE 8. UPPER GATE DRIVE
where QGATE is the maximum total gate charge of the
MOSFET, CBOOT is the bootstrap capacitance, VBOOT1 is
the bootstrap voltage immediately before turn-on, and
VBOOT2 is the bootstrap voltage immediately after turn-on.
The bootstrap capacitor begins its refresh cycle when the
gate drive begins to turn off the MOSFET. A refresh cycle
ends when the MOSFET is turned on again, which varies
depending on the switching frequency and duty cycle.
The minimum bootstrap capacitance can be calculated by
rearranging Equation 19 and solving for CBOOT.
CBOO
T
≥
QGATE
V-----B----O----O-----T---1-----–----V----B----O-----O----T----2-
(EQ. 20)
Typical gate charge values for MOSFETs considered in
these types of applications range from 20–100nC. Since the
voltage drop across D2 is offset by the voltage drop across
D1, VBOOT1 is simply VCC (+5V). A good rule is to keep the
voltage drop across the bootstrap capacitor no greater than
1V during the on-time of the MOSFET. Initial calculations
with VBOOT2 no less than 4V will quickly help narrow the
bootstrap capacitor range.
For example, consider a MOSFET is chosen with a
maximum gate charge, Qg, of 100nC. Limiting the voltage
drop across the bootstrap capacitor to 1V results in a value
of no less than 0.1µF. The tolerance of the ceramic capacitor
should also be considered when selecting the final bootstrap
capacitance value.
A fast recovery diode is recommended when selecting a
bootstrap diode to reduce the impact of reverse recovery
charge loss. Otherwise, the recovery charge, QRR, would
have to be added to the gate charge of the MOSFET and
taken into consideration when calculating the minimum
bootstrap capacitance. Employing a Schottky diode over a
standard diode will also increase the gate drive voltage
available to enhance the MOSFET.
11
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| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ISL6528.PDF ] | |
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