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PDF ISL6526 Data sheet ( Hoja de datos )
| Número de pieza | ISL6526 | |
| Descripción | Single Synchronous Buck Pulse-Width Modulation (PWM) Controller | |
| Fabricantes | Intersil Corporation | |
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®
Data Sheet
Single Synchronous Buck Pulse-Width
Modulation (PWM) Controller
The ISL6526 makes simple work out of implementing a
complete control and protection scheme for a DC-DC
stepdown converter. Designed to drive N-Channel
MOSFETs in a synchronous buck topology, the ISL6526
integrates the control, output adjustment, monitoring and
protection functions into a single package.
The ISL6526 provides simple, single feedback loop, voltage-
mode control with fast transient response. The output
voltage can be precisely regulated to as low as 0.8V, with a
maximum tolerance of ±1.5% over temperature and line
voltage variations. A fixed frequency oscillator reduces
design complexity, while balancing typical application cost
and efficiency.
The error amplifier features a 15MHz gain-bandwidth
product and 6V/µs slew rate which enables high converter
bandwidth for fast transient performance. The resulting
PWM duty cycles range from 0% to 100%.
Protection from overcurrent conditions is provided by
monitoring the rDS(ON) of the upper MOSFET to inhibit PWM
operation appropriately. This approach simplifies the
implementation and improves efficiency by eliminating the
need for a current sense resistor.
Ordering Information
TEMP
PART NUMBER RANGE (oC)
PACKAGE PKG DWG. #
ISL6526CB
0 to 70 14 Lead SOIC M14.15
ISL6526ACB
0 to 70 14 Lead SOIC M14.15
ISL6526CR
0 to 70 16 Lead 5x5 QFN L16.5x5B
ISL6526ACR
0 to 70 16 Lead 5x5 QFN L16.5x5B
ISL6526IB
-40 to 85 14 Lead SOIC M14.15
ISL6526AIB
-40 to 85 14 Lead SOIC M14.15
ISL6526IR
-40 to 85 16 Lead 5x5 QFN L16.5x5B
ISL6526AIR
-40 to 85 16 Lead 5x5 QFN L16.5x5B
ISL6526EVAL1 ISL6526 SOIC Evaluation Board
ISL6526EVAL2 ISL6526 QFN Evaluation Board
ISL6526AEVAL1 ISL6526A SOIC Evaluation Board
ISL6526AEVAL2 ISL6526A QFN Evaluation Board
ISL6526
July 2003
FN9055.3
Features
• Operates from 3.3V to 5V Input
• 0.8V to VIN Output Range
- 0.8V Internal Reference
- ±1.5% Over Load, Line Voltage and Temperature
• Drives N-Channel MOSFETs
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
• Fast Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Cycle
• Lossless, Programmable Overcurrent Protection
- Uses Upper MOSFET’s rDS(on)
• Converter can Source and Sink Current
• Small Converter Size
- Internal Fixed Frequency Oscillator
- ISL6526: 300kHz
- ISL6526A: 600kHz
• Internal Soft-Start
• 14 Lead SOIC or 16 Lead, 5x5 QFN
• QFN Package:
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
Applications
• Power Supplies for Microprocessors
- PCs
- Embedded Controllers
• Subsystem Power Supplies
- PCI/AGP/GTL+ Busses
- ACPI Power Control
- DDR SDRAM Bus Termination Supply
• Cable Modems, Set Top Boxes, and DSL Modems
• DSP and Core Communications Processor Supplies
• Memory Supplies
• Personal Computer Peripherals
• Industrial Power Supplies
• 3.3V-Input DC-DC Regulators
• Low-Voltage Distributed Power Supplies
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6526
Electrical Specifications
PARAMETER
GATE DRIVERS
Upper Gate Source Current
Upper Gate Sink Current
Lower Gate Source Current
Lower Gate Sink Current
PROTECTION / DISABLE
OCSET Current Source
Disable Threshold
Recommended Operating Conditions, unless otherwise noted VCC = 3.3V±5% and TA = 25°C (Continued)
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
IUGATE-SRC VBOOT - VPHASE = 5V, VUGATE = 4V
IUGATE-SNK
ILGATE-SRC VVCC = 3.3V, VLGATE = 4V
ILGATE-SNK
IOCSET
VDISABLE
Commercial
Industrial
- -1 -
-1-
- -1 -
-2-
A
A
A
A
18 20 22
µA
16 20 22
µA
-
- 0.8
V
Functional Pin Description
14 LEAD (SOIC)
TOP VIEW
GND 1
LGATE 2
CPVOUT 3
CT1 4
CT2 5
OCSET 6
FB 7
14 UGATE
13 BOOT
12 PHASE
11 VCC
10 CPGND
9 ENABLE
8 COMP
16 LEAD 5X5 (QFN)
TOP VIEW
16 15 14 13
CPVOUT 1
CT1 2
CT2 3
12 PHASE
11 VCC
10 CPGND
OCSET 4
9 NC
5678
VCC
This pin provides the bias supply for the ISL6526. Connect a
well-decoupled 3.3V supply to this pin.
COMP and FB
COMP and FB are the available external pins of the error
amplifier. The FB pin is the inverting input of the internal
error amplifier and the COMP pin is the error amplifier
output. These pins are used to compensate the voltage-
control feedback loop of the converter.
GND
This pin represents the signal and power ground for the IC.
Tie this pin to the ground island/plane through the lowest
impedance connection available.
PHASE
Connect this pin to the upper MOSFET’s source. This pin is
used to monitor the voltage drop across the upper MOSFET
for overcurrent protection.
UGATE
Connect this pin to the upper MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the upper
MOSFET. This pin is also monitored by the adaptive shoot-
through protection circuitry to determine when the upper
MOSFET has turned off.
BOOT
This pin provides ground referenced bias voltage to the
upper MOSFET driver. A bootstrap circuit is used to create a
voltage suitable to drive a logic-level N-Channel MOSFET.
LGATE
Connect this pin to the lower MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the lower
MOSFET. This pin is also monitored by the adaptive shoot-
through protection circuitry to determine when the lower
MOSFET has turned off.
OCSET
Connect a resistor (ROCSET) from this pin to the drain of the
upper MOSFET (VIN). ROCSET, an internal 20µA current
source (IOCSET), and the upper MOSFET on-resistance
(rDS(ON)) set the converter overcurrent (OC) trip point
according to the following equation:
IPEAK = I--O-----C----S---r-E-D---T-S---x-(--RO-----ON----C)----S----E----T--
An overcurrent trip cycles the soft-start function.
5
5 Page 
ISL6526
The maximum RMS current required by the regulator may be
closely approximated through the following equation:
IRMSMAX =
V---V--O--I--UN---T-
×
IO
UTM
A
2
X
+
1--1--2--
×
-V----I-N--L---–--×---V--f--Os----U---T-
×
V---V--O--I--UN---T-
2
For a through hole design, several electrolytic capacitors may
be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
regard to the capacitor surge currentrating. These capacitors
must be capable of handling the surge-current at power-up.
Some capacitor series available from reputable manufacturers
are surge current tested.
MOSFET Selection/Considerations
The ISL6526 requires two N-Channel power MOSFETs.
These should be selected based upon rDS(ON), gate supply
requirements, and thermal management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss components;
conduction loss and switching loss. The conduction losses are
the largest component of power dissipation for both the upper
and the lower MOSFETs. These losses are distributed between
the two MOSFETs according to duty factor. The switching
losses seen when sourcing current will be different from the
switching losses seen when sinking current. When sourcing
current, the upper MOSFET realizes most of the switching
losses. The lower switch realizes most of the switching losses
when the converter is sinking current (see equations on next
page). These equations assume linear voltage-current
transitions and do not adequately model power loss due the
reverse-recovery of the upper and lower MOSFET’s body
diode. The gate-charge losses are dissipated by the ISL6526
and don't heat the MOSFETs. However, large gate-charge
increases the switching interval, tSW which increases the
MOSFET switching losses. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate heatsink
may be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
Losses while Sourcing current
PUPPER = Io2 × rDS(ON) × D + 12-- ⋅ Io × VIN × tSW × fs
PLOWER = Io2 x rDS(ON) x (1 - D)
Losses while Sinking current
PUPPER = Io2 x rDS(ON) x D
PLOWER = Io2 × rDS(ON) × (1 – D) + 12-- ⋅ Io × VIN × tSW × fs
Where: D is the duty cycle = VOUT / VIN,
tSW is the combined switch ON and OFF time, and
fs is the switching frequency.
Given the reduced available gate bias voltage (5V), logic-
level or sub-logic-level transistors should be used for both N-
MOSFETs. Caution should be exercised with devices
exhibiting very low VGS(ON) characteristics. The shoot-
through protection present aboard the ISL6526 may be
circumvented by these MOSFETs if they have large parasitic
impedences and/or capacitances that would inhibit the gate
of the MOSFET from being discharged below its threshold
level before the complementary MOSFET is turned on.
Bootstrap Component Selection
External bootstrap components, a diode and capacitor, are
required to provide sufficient gate enhancement to the upper
MOSFET. The internal MOSFET gate driver is supplied by
the external bootstrap circuitry as shown in Figure 7. The
boot capacitor, CBOOT, develops a floating supply voltage
referenced to the PHASE pin. This supply is refreshed each
cycle, when DBOOT conducts, to a voltage of CPVOUT less
the boot diode drop, VD, plus the voltage rise across
QLOWER.
ISL6526
CPVOUT
DBOOT
BOOT
+
VD
-
CBOOT
VIN
UGATE
PHASE
QUPPER
NOTE:
VG-S = VCC -VD
+-
LGATE
QLOWER
GND
NOTE:
VG-S = VCC
FIGURE 7. UPPER GATE DRIVE BOOTSTRAP
Just after the PWM switching cycle begins and the charge
transfer from the bootstrap capacitor to the gate capacitance
is complete, the voltage on the bootstrap capacitor is at its
lowest point during the switching cycle. The charge lost on
the bootstrap capacitor will be equal to the charge
transferred to the equivalent gate-source capacitance of the
upper MOSFET as shown:
QGATE = CBOOT × (VBOOT1 – VBOOT2)
where QGATE is the maximum total gate charge of the upper
MOSFET, CBOOT is the bootstrap capacitance, VBOOT1 is
the bootstrap voltage immediately before turn-on, and
VBOOT2 is the bootstrap voltage immediately after turn-on.
The bootstrap capacitor begins its refresh cycle when the gate
drive begins to turn-off the upper MOSFET. A refresh cycle
ends when the upper MOSFET is turned on again, which
varies depending on the switching frequency and duty cycle.
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ISL6526.PDF ] | |
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