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PDF ISL6524 Data sheet ( Hoja de datos )
| Número de pieza | ISL6524 | |
| Descripción | VRM8.5 PWM and Triple Linear Power System Controller | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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TM
Data Sheet
January 2002
ISL6524
FN9015.1
VRM8.5 PWM and Triple Linear Power
System Controller
The ISL6524 provides the power control and protection for
four output voltages in high-performance microprocessor
and computer applications. The IC integrates one PWM
controller and three linear controllers, as well as the
monitoring and protection functions into a 28-pin SOIC
package. The PWM controller regulates the microprocessor
core voltage with a synchronous-rectified buck converter.
One linear controller supplies the computer system’s AGTL+
1.2V bus power. The other two linear controllers regulate
power for the 1.5V AGP bus and the 1.8V power for the chip
set core voltage and/or cache memory circuits.
The ISL6524 includes an Intel VRM8.5 compatible, TTL
5-input digital-to-analog converter (DAC) that adjusts the
microprocessor core-targeted PWM output voltage from
1.050V to 1.825V in 25mV steps. The precision reference
and voltage-mode control provide ±1% static regulation. The
linear regulators use external N-channel MOSFETs or
bipolar NPN pass transistors to provide fixed output voltages
of 1.2V ±3% (VOUT2), 1.5V ±3% (VOUT3) and 1.8V ±3%
(VOUT4).
The ISL6524 monitors all the output voltages. A delayed-
rising VTT (VOUT2 output) Power Good signal is issued
before the core PWM starts to ramp up. Another system
Power Good signal is issued when the core is within ±10% of
the DAC setting and all other outputs are above their under-
voltage levels. Additional built-in overvoltage protection for
the core output uses the lower MOSFET to prevent output
voltages above 115% of the DAC setting. The PWM
controllers’ overcurrent function monitors the output current
by using the voltage drop across the upper MOSFET’s
rDS(ON), eliminating the need for a current sensing resistor.
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
ISL6524CB
0 to 70 28 Ld SOIC
ISL6524EVAL1
Evaluation Board
PKG.
NO.
M28.3
Features
• Provides 4 Regulated Voltages
- Microprocessor Core, AGTL+ Bus, AGP Bus Power,
and North/South Bridge Core
• Drives N-Channel MOSFETs
• Linear Regulator Drives Compatible with both MOSFET
and Bipolar Series Pass Transistors
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
• Fast PWM Converter Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Ratio
• Excellent Output Voltage Regulation
- Core PWM Output: ±1% Over Temperature
- All Other Outputs: ±3% Over Temperature
• VRM8.5 TTL-Compatible 5-Bit DAC Microprocessor Core
Output Voltage Selection
- Wide Range - 1.050V to 1.825V
• Power-Good Output Voltage Monitors
- Separate delayed VTT Power Good
• Overcurrent Fault Monitor
- Switching Regulator Doesn’t Require Extra Current
Sensing Element, Uses MOSFET’s rDS(ON)
• Small Converter Size
- Constant Frequency Operation
- 200kHz Internal Oscillator
Applications
• Motherboard Power Regulation for Computers
Pinout
ISL6524 (SOIC)
TOP VIEW
DRIVE2 1
FIX 2
VID3 3
VID2 4
VID1 5
VID0 6
VID25 7
PGOOD 8
VTTPG 9
FAULT/RT 10
VSEN2 11
SS24 12
SS13 13
VSEN4 14
28 VCC
27 UGATE
26 PHASE
25 LGATE
24 PGND
23 OCSET
22 VSEN1
21 FB
20 COMP
19 VSEN3
18 DRIVE3
17 GND
16 VAUX
15 DRIVE4
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1 page  
ISL6524
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3 (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
Gain-Bandwidth Product
GBWP Note 2
- 15 - MHz
Slew Rate
SR COMP = 10pF, Note 2
- 6 - V/µs
PWM CONTROLLERS GATE DRIVERS
UGATE Source
UGATE Sink
LGATE Source
LGATE Sink
PROTECTION
IUGATE
RUGATE
ILGATE
RLGATE
VCC = 12V, VUGATE = 6V
VGATE-PHASE = 1V
VCC = 12V, VLGATE = 1V
VLGATE = 1V
-1-
- 1.7 3.5
-1-
- 1.4 3.0
A
Ω
A
Ω
FAULT Sourcing Current
OCSET Current Source
Soft-Start Current
POWER GOOD
IOVP
IOCSET
ISS13,24
VFAULT/RT = 2.0V
VOCSET = 4.5VDC
VSS13,24 = 2.0VDC
- 8.5 -
170 200 230
- 28 -
mA
µA
µA
VSEN1 Upper Threshold
(VSEN1/DACOUT)
VSEN1 Rising
108 - 110
%
VSEN1 Undervoltage
(VSEN1/DACOUT)
VSEN1 Rising
92 - 94
%
VSEN1 Hysteresis (VSEN1/DACOUT)
VSEN1 Falling
-2-
%
PGOOD Voltage Low
VSEN2 Undervoltage
VPGOOD
IPGOOD = -4mA
VSEN2 Rising
- - 0.8
1.08
V
V
VSEN2 Hysteresis
VSEN2 Falling
- 48 -
mV
VTTPG Voltage Low
NOTE:
2. Guaranteed by design
VVTTPG IVTTPG = -4mA
- - 0.8 V
Typical Performance Curves
1000
100
RT PULLUP
TO +12V
10
RT PULLDOWN TO VSS
10 100
SWITCHING FREQUENCY (kHz)
FIGURE 4. RT RESISTANCE vs FREQUENCY
1000
100
CUGATE = CLGATE = C
VIN = 5V
80 VCC = 12V
C = 4800pF
60
C = 3600pF
40 C = 1500pF
20
C = 660pF
0
100 200 300 400 500 600 700 800 900 1000
SWITCHING FREQUENCY (kHz)
FIGURE 5. BIAS SUPPLY CURRENT vs FREQUENCY
5
5 Page 
ISL6524
Dedicate another solid layer as a power plane and break this
plane into smaller islands of common voltage levels. The
power plane should support the input power and output
power nodes. Use copper filled polygons on the top and
bottom circuit layers for the PHASE node, but do not
unnecessarily oversize this particular island. Since the
PHASE node is subject to very high dV/dt voltages, the stray
capacitor formed between these island and the surrounding
circuitry will tend to couple switching noise. Use the
remaining printed circuit layers for small signal wiring. The
wiring traces from the control IC to the MOSFET gate and
source should be sized to carry 2A peak currents.
+5VIN
LIN
CIN
+3.3VIN
VOUT2
Q3
COUT2
CSS24,13
VOUT3
+12V
CVCC
VCC GND
COCSET
OCSET
DRIVE2
UGATE
ROCSET
Q1
LOUT
PHASE
VOUT1
SS24
SS13
LGATE
Q2
ISL6524
COUT1
CR1
VOUT4
COUT3
Q4
DRIVE3 DRIVE4
PGND
COUT4
Q5
+3.3VIN
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
VIA/THROUGH-HOLE CONNECTION TO GROUND PLANE
FIGURE 10. PRINTED CIRCUIT BOARD POWER PLANES AND
ISLANDS
PWM1 Controller Feedback Compensation
The PWM controller uses voltage-mode control for output
regulation. This section highlights the design consideration for a
voltage-mode controller requiring external compensation.
Figure 11 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(VOUT) is regulated to the Reference voltage level. The
reference voltage level is the DAC output voltage (DACOUT)
for the PWM. The error amplifier output (VE/A) is compared with
the oscillator (OSC) triangular wave to provide a pulse-width
modulated wave with an amplitude of VIN at the PHASE node.
The PWM wave is smoothed by the output filter (LO and CO).
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A. This function is dominated by a DC
Gain, given by VIN/VOSC, and shaped by the output filter, with
a double pole break frequency at FLC and a zero at FESR.
∆ VOSC
OSC
PWM
COMP
-
+
VIN
DRIVER
LO VOUT
DRIVER
PHASE
CO
VE/A
ZFB
-
+
ERROR
AMP
ZIN
REFERENCE
ESR
(PARASITIC)
DETAILED COMPENSATION COMPONENTS
C2
C1 R2
ZFB
VOUT
ZIN
C3 R3
COMP
ISL6524
FB
-
+
DACOUT
R1
FIGURE 11. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
Modulator Break Frequency Equations
FLC=
-------------------1--------------------
2π × LO × CO
FESR=
--------------------1--------------------
2π × ESR × CO
The compensation network consists of the error amplifier
(internal to the ISL6524) and the impedance networks ZIN and
ZFB. The goal of the compensation network is to provide a
closed loop transfer function with high 0dB crossing frequency
(f0dB) and adequate phase margin. Phase margin is the
difference between the closed loop phase at f0dB and 180o.
The equations below relate the compensation network’s poles,
zeros and gain to the components (R1, R2, R3, C1, C2, and
C3) in Figure 11. Use these guidelines for locating the poles
and zeros of the compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1STZero Below Filter’s Double Pole (~75% FLC)
3. Place 2ND Zero at Filter’s Double Pole
4. Place 1ST Pole at the ESR Zero
5. Place 2ND Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ISL6524.PDF ] | |
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