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PDF 74AC175 Data sheet ( Hoja de datos )
| Número de pieza | 74AC175 | |
| Descripción | QUAD D FLIP-FLOP WITH MASTER RESET | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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Data sheet acquired from Harris Semiconductor
SCHS242
September 1998
CD74AC175,
CD74ACT175
Quad D Flip-Flop with Reset
[ /Title
(CD74
AC175
,
CD74
ACT17
5
)
/Sub-
ject
(Quad
D Flip-
Flop
with
Reset)
/Autho
r ()
/Key-
words
(Har-
ris
Semi-
con-
ductor,
Advan
ced
CMOS
, Harris
Semi-
con-
ductor,
Advan
ced
TTL)
/Cre-
ator ()
/DOCI
NFO
Features
• Buffered Inputs
• Typical Propagation Delay
- 6.4ns at VCC = 5V, TA = 25oC, CL = 50pF
• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015
• SCR-Latchup-Resistant CMOS Process and Circuit
Design
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
• Balanced Propagation Delays
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
• ±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
- Drives 50Ω Transmission Lines
Description
The CD74AC175 and CD74ACT175 are quad D flip-flops
with reset that utilize the Harris Advanced CMOS Logic tech-
nology. Information at the D input is transferred to the Q and
Q outputs on the positive-going edge of the clock pulse. All
four flip-flops are controlled by a common clock (CP) and a
common reset (MR). Resetting is accomplished by a LOW
logic level independent of the clock.
Ordering Information
PART
NUMBER
TEMP.
RANGE (oC)
PACKAGE
PKG.
NO.
CD74AC175E
-55 to 125
16 Ld PDIP E16.3
CD74ACT175E
-55 to 125
16 Ld PDIP E16.3
CD74AC175M
-55 to 125
16 Ld SOIC M16.15
CD74ACT175M
-55 to 125
16 Ld SOIC M16.15
NOTES:
13. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
14. Wafer and die for this part number is available which meets all elec-
trical specifications. Please contact your local sales office or Harris
customer service for ordering information.
Pinout
CD74AC175, CD74ACT175
(PDIP, SOIC)
TOP VIEW
MR 1
Q0 2
Q0 3
D0 4
D1 5
Q1 6
Q1 7
GND 8
16 VCC
15 Q3
14 Q3
13 D3
12 D2
11 Q2
10 Q2
9 CP
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
Copyright © Harris Corporation 1998
1
File Number 1964.1
1 page  
CD74AC175, CD74ACT175
Prerequisite For Switching Function
PARAMETER
AC TYPES
Data to CP Set-Up Time
Hold Time
Removal Time, MR to CP
MR Pulse Width
CP Pulse Width
CP Frequency
ACT TYPES
Data to CP Set-Up Time
Hold Time
Removal Time, MR to CP
MR Pulse Width
Clock Pulse Width
CP Frequency
NOTES:
20. 3.3V Min is at 3V.
21. 5V Min is at 4.5V.
SYMBOL
VCC (V)
tSU
tH
tREM
tW
tW
fMAX
1.5
3.3
(Note 8)
5
(Note 9)
1.5
3.3
5
1.5
3.3
5
1.5
3.3
5
1.5
3.3
5
1.5
3.3
5
tSU
tH
tREM
tW
tW
fMAX
5
(Note 9)
5
5
5
5
5
-40oC TO 85oC
MIN MAX
2-
2-
2-
2-
2-
2-
1-
1-
1-
44 -
4.9 -
3.5 -
55 -
6.1 -
4.4 -
9-
81 -
114 -
2-
2-
1-
3.5 -
4.4 -
114 -
-55oC TO 125oC
MIN MAX
UNITS
2 - ns
2 - ns
2 - ns
2 - ns
2 - ns
2 - ns
1 - ns
1 - ns
1 - ns
50 - ns
5.6 - ns
4 - ns
63 - ns
7 - ns
5 - ns
8 - MHz
71 - MHz
100 - MHz
2 - ns
2 - ns
1 - ns
4 - ns
5 - ns
114 - MHz
Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case)
-40oC TO 85oC
PARAMETER
AC TYPES
SYMBOL
VCC (V)
MIN
TYP MAX
Propagation Delay, CP to Q, Q
tPLH, tPHL
1.5
3.3
(Note 11)
-
4.4
- 139
- 15.5
5
(Note 12)
3.2
- 11.1
-55oC TO 125oC
MIN TYP MAX
UNITS
- - 153 ns
4.3 - 17.1 ns
3.1 - 12.2 ns
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 74AC175.PDF ] | |
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