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PDF DSP56F802 Data sheet ( Hoja de datos )
| Número de pieza | DSP56F802 | |
| Descripción | DSP56F802 16-bit Digital Signal Processor | |
| Fabricantes | Motorola Inc | |
| Logotipo |  |
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DSP56F802/D
Rev. 0, 1/2002
DSP56F802
Preliminary Technical Data
DSP56F802 16-bit Digital Signal Processor
• Up to 40 MIPS operation at 80 MHz core
frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• MCU-friendly instruction set supports both
DSP and controller functions: MAC, bit
manipulation unit, 14 addressing modes
• 8K × 16-bit words Program Flash
• 1K × 16-bit words Program RAM
• 2K × 16-bit words Data Flash
• 1K × 16-bit words Data RAM
• 2K × 16-bit words Boot Flash
• Hardware DO and REP loops
• 6-channel PWM Module with fault input
• Two 12-bit ADCs (1 x 2 channel, 1 x 3 channel)
• Serial Communications Interface (SCI)
• Two General Purpose Quad Timers with 2
external outputs
• JTAG/OnCETM port for debugging
• 4 shared GPIO
• On-chip relaxation oscillator
• 32-pin LQFP Package
PWM Outputs
6
Fault A0
2 A/D1
3
A/D2 ADC
VREF
PWMA
RESET
5
JTAG/
OnCE
Port
VCAPC VDD
22
VSS* VDDA
3
VSSA
Digital Reg Analog Reg
Low Voltage
Supervisor
Interrupt
Controller
Program Controller
and
Hardware Looping Unit
Address
Generation
Unit
Data ALU
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Bit
Manipulation
Unit
Quad Timer C
Quad Timer D
2 or GPIO
Program Memory
8188 x 16 Flash
1024 x 16 SRAM
Boot Flash
2048x 16 Flash
Data Memory
2048 x 16 Flash
1024 x 16 SRAM
SCI0
or
2 GPIO
COP/
Watchdog
Application-
Specific
Memory &
Peripherals
••
PAB
PDB
•
XDB2
Relaxation
Oscillator
.
• CGDB
XAB1
XAB2
•
•
•
•
INTERRUPT
IPBB
CONTROLS CONTROLS
16-Bit
DSP56800
Core
16 16
COP RESET
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
IPBus Bridge
(IPBB)
*includes TCS pin which is reserved for factory use and is tied to VSS
PLL
Figure 1. DSP56F802 Block Diagram
© Motorola, Inc., 2002. All rights reserved.
1 page  
Data Sheet Conventions
1.5 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
“asserted”
A high true (active high) signal is high or a low true (active low) signal is low.
“deasserted” A high true (active high) signal is low or a low true (active low) signal is high.
Examples:
Signal/Symbol
Logic State
Signal State
Voltage1
PIN
True
Asserted
VIL/VOL
PIN
False
Deasserted
VIH/VOH
PIN
True
Asserted
VIH/VOH
PIN
False
Deasserted
1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
VIL/VOL
MOTOROLA
DSP56F802 Preliminary Technical Data
5
5 Page 
General Characteristics
Part 3 Specifications
3.1 General Characteristics
The DSP56F802 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs.
The term “5-volt tolerant” refers to the capability of an I/O pin, built on a 3.3V compatible process
technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture
of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V-
compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10%
during normal operation without causing damage). This 5V tolerant capability therefore offers the power
savings of 3.3V I/O levels while being able to receive 5V levels without being damaged.
Absolute maximum ratings given in Table 12 are stress ratings only, and functional operation at the
maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.
The DSP56F802 DC and AC electrical specifications are preliminary and are from design simulations.
These specifications may not be fully tested or guaranteed at this early stage of the product life cycle.
Finalized specifications will be published after complete characterization and device qualifications have
been completed.
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate voltage level.
Table 12. Absolute Maximum Ratings
Characteristic
Symbol
Min
Supply voltage
All other input voltages, excluding Analog inputs
Analog Inputs ANAx, VREF
Current drain per pin excluding VDD, VSS, & PWM ouputs
Current drain per pin for PWM outputs
Junction temperature
Storage temperature range
VDD
VIN
VIN
I
I
TJ
TSTG
VSS – 0.3
VSS – 0.3
VSS – 0.3
—
—
—
-55
Max
VSS + 4.0
VSS + 5.5V
VDDA + 0.3V
10
20
150
150
Unit
V
V
V
mA
mA
°C
°C
MOTOROLA
DSP56F802 Preliminary Technical Data
11
11 Page | ||
| Páginas | Total 32 Páginas | |
| PDF Descargar | [ Datasheet DSP56F802.PDF ] | |
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