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PDF HY62256ALP Data sheet ( Hoja de datos )
| Número de pieza | HY62256ALP | |
| Descripción | 32Kx8bit CMOS SRAM | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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HY62256A Series
32Kx8bit CMOS SRAM
DESCRIPTION
FEATURES
The HY62256A is a high-speed, low power and
• Fully static operation and Tri-state output
32,786 x 8-bits CMOS Static Random Access
• TTL compatible inputs and outputs
Memory fabricated using Hyundai's high
• Low power consumption
performance CMOS process technology. The
HY62256A has a data retention mode that
• Battery backup(L/LL-part)
- 2.0V(min.) data retention
guarantees data to remain valid at the minimum
• Standard pin configuration
power supply voltage of 2.0 volt. Using the CMOS
- 28 pin 600 mil PDIP
technology, supply voltages from 2.0 to 5.5volt
- 28 pin 330mil SOP
has little effect on supply current in the data
retention mode. The HY62256A is suitable for use
in low voltage operation and battery back-up
mapplication.
oProduct Voltage Speed
.cNo. (V) (ns)
HY62256A
5.0 55/70/85
Note 1. Current value is max.
Operation
Current(mA)
50
- 28 pin 8x13.4 mm TSOP-I
(Standard and Reversed)
Standby Current(uA)
L LL
1mA 100
25
Temperature
(°C)
0~70(Normal)
t4UPIN CONNECTION
eeA14
A12
A7
hA6
A5
A4
A3
SA2
A1
A0
I/O1
taI/O2
I/O3
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
Vcc
/WE
A13
A8
A9
A11
/OE
A14
A12
A7
A6
A5
A4
A3
21 A10 A2
1
2
3
4
5
6
7
8
20 /CS A1 9
19
18
17
16
15
I/O8 A0
I/O7
I/O6
I/O5
I/O4
I/O1
I/O2
I/O3
Vss
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
aPDIP
SOP
Vcc
/WE
A13
A8
A9
A11
/OE
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
/OE
A11
A9
A8
A13
/WE
Vcc
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 A10
27 /CS
26 I/O8
25 I/O7
24 I/O6
23 I/O5
22 I/O4
21 Vss
20 I/O3
19 I/O2
18 I/O1
17 A0
16 A1
15 A2
TSOP-I(Standard)
A3
A4
A5
A6
A7
A12
A14
Vcc
/WE
A13
A8
A9
A11
/OE
14
13
12
11
10
9
8
7
6
5
4
3
2
1
15 A2
16 A1
17 A0
18 I/O1
19 I/O2
20 I/O3
21 Vss
22 I/O4
23 I/O5
24 I/O6
25 I/O7
26 I/O8
27 /CS
28 A10
TSOP-I(Reversed)
.DPIN DESCRIPTION
wPin Name
/CS
w/WE
w/OE
Pin Function
Chip Select
Write Enable
Output Enable
BLOCK DIAGRAM
A0 ROW DECODER
MEMORY ARRAY
I/O1
A0 ~ A14
omI/O1 ~ I/O8
.cVcc
et4UVss
Address Inputs
Data Input/Output
Power(+5.0V)
Ground
A14
/CS
/OE
/WE
512x512
I/O8
.DataSheThis document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
wresponsibility for use of circuits described. No patent licenses are implied.
wwRev.02 /Jun.99
Hyundai Semiconductor
1 page  
HY62256A Series
Note(READ CYCLE):
1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not
referenced to output voltage levels.
2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min. both for a given device
and from device to device.
3. /WE is high for the read cycle.
READ CYCLE 2
ADDR
Data
Out
tAA
tOH
Previous Data
tRC
Data Valid
tOH
Note(READ CYCLE):
1. /WE is high for the read cycle.
2. Device is continuously selected /CS= VIL.
3. /OE =VIL.
WRITE CYCLE 1(/OE Clocked)
ADDR
tWC
OE
CS
WE
Data In
Data
Out
tAS
tOHZ
tAW
tCW
tWP tWR
tDW
tDH
Data Valid
Rev.02 /Jun.99
5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet HY62256ALP.PDF ] | |
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