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PDF DS90CR218 Data sheet ( Hoja de datos )
| Número de pieza | DS90CR218 | |
| Descripción | +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link Receiver - 75 MHz | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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May 2002
DS90CR218
+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel
Link Receiver - 75 MHz
General Description
The DS90CR217 (see DS90CR217/218A datasheet) trans-
mitter converts 21 bits of CMOS/TTL data into three LVDS
(Low Voltage Differential Signaling) data streams. A phase-
locked transmit clock is transmitted in parallel with the data
streams over a fourth LVDS link. Every cycle of the transmit
clock 21 bits of input data are sampled and transmitted. The
DS90CR218 receiver converts the three LVDS data streams
back into 21 bits of CMOS/TTL data. At a transmit clock
frequency of 75 MHz, 21 bits of TTL data are transmitted at
a rate of 525 Mbps per LVDS data channel. Using a 75 MHz
clock, the data throughput is 1.575 Gbit/s (197 Mbytes/sec).
Complete specifications for the DS90CR217 are located in
the DS90CR217/DS90CR218A datasheet. The DS90CR217
supports clock rates from 20 to 85 MHz.
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high-speed TTL interfaces.
Features
n 20 to 75 MHz shift clock support
n 50% duty cycle on receiver output clock
n Best-in-Class Set & Hold Times on TxINPUTs and
RxOUTPUTs
n Low power consumption
n Tx + Rx Powerdown mode <400µW (max)
n ±1V common-mode range (around +1.2V)
n Narrow bus reduces cable size and cost
n Up to 1.575 Gbps throughput
n Up to 197 Mbytes/sec bandwidth
n 345 mV (typ) swing LVDS devices for low EMI
n PLL requires no external components
n Rising edge data strobe
n Compatible with TIA/EIA-644 LVDS standard
n Low profile 48-lead TSSOP package
Block Diagrams
DS90CR217
DS90CR218
Order Number DS90CR217MTD
See NS Package Number MTD48
(See DS90CR217/DS90CR218A Datasheet)
10087101
Order Number DS90CR218MTD
See NS Package Number MTD48
10087127
© 2002 National Semiconductor Corporation DS100871
www.national.com
1 page  
AC Timing Diagrams (Continued)
10087110
FIGURE 3. DS90CR218 (Receiver) Setup/Hold and High/Low Times
10087112
FIGURE 4. DS90CR218 (Receiver) Clock In to Clock Out Delay
10087114
FIGURE 5. DS9OCR218 (Receiver) Phase Lock Loop Set Time
5 www.national.com
5 Page 
Applications Information (Continued)
The CHANNEL LINK chipset is designed to protect itself
from accidental loss of power to either the transmitter or
receiver. If power to the transmit board is lost, the receiver
clocks (input and output) stop. The data outputs (RxOUT)
retain the states they were in when the clocks stopped.
When the receiver board loses power, the receiver inputs are
shorted to VCC through an internal diode. Current is limited
(5 mA per input) by the fixed current mode drivers, thus
avoiding the potential for latchup when powering the device.
FIGURE 12. Single-Ended and Differential Waveforms
10087126
11 www.national.com
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet DS90CR218.PDF ] | |
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