PDF DS90CF366 Data sheet ( Hoja de datos )

Número de pieza	DS90CF366
Descripción	+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link85 MHz/ +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link85 MHz
Fabricantes	National Semiconductor
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No Preview Available ! November 1999 DS90CF386/DS90CF366 +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link— 85 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link— 85 MHz General Description The DS90CF386 receiver converts the four LVDS data streams (Up to 2.38 Gbps throughput or 297.5 Megabytes/ sec bandwidth) back into parallel 28 bits of CMOS/TTL data (24 bits of RGB and 4 bits of Hsync, Vsync, DE and CNTL). Also available is the DS90CF366 that converts the three LVDS data streams (Up to 1.78 Gbps throughput or 223 Megabytes/sec bandwidth) back into parallel 21 bits of CMOS/TTL data (18 bits of RGB and 3 bits of Hsync, Vsync and DE). Both Receivers’ outputs are Falling edge strobe. A Rising edge or Falling edge strobe transmitter (DS90C385/ DS90C365) will interoperate with a Falling edge strobe Re- ceiver without any translation logic. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces. Features n 20 to 85 MHz shift clock support n Rx power consumption <142 mW (typ) @85MHz Grayscale n Rx Power-down mode <1.44 mW (max) n ESD rating >7 kV (HBM), >700V (EIAJ) n Supports VGA, SVGA, XGA and Single Pixel SXGA. n PLL requires no external components n Compatible with TIA/EIA-644 LVDS standard n Low profile 56-lead or 48-lead TSSOP package Block Diagrams DS90CF386 DS90CF366 Order Number DS90CF386MTD See NS Package Number MTD56 DS101085-27 Order Number DS90CF366MTD See NS Package Number MTD48 DS101085-28 TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS101085 www.national.com 1 page AC Timing Diagrams (Continued) FIGURE 3. “16 Grayscale” Test Pattern (DS90CF366)(Notes 5, 6, 7, 8) DS101085-3 Note 5: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. Note 6: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display. Note 7: Figures 1, 3 show a falling edge data strobe (TxCLK IN/RxCLK OUT). Note 8: Recommended pin to signal mapping. Customer may choose to define differently. DS101085-4 FIGURE 4. DS90CF386/DS90CF366 (Receiver) CMOS/TTL Output Load and Transition Times DS101085-5 FIGURE 5. DS90CF386/DS90CF366 (Receiver) Setup/Hold and High/Low Times 5 www.national.com 5 Page DS90CF386 Pin Description — 24-Bit FPD Link Receiver Pin Name RxIN+ RxIN− RxOUT RxCLK IN+ RxCLK IN− RxCLK OUT PWR DOWN V CC GND PLL V CC PLL GND LVDS V CC LVDS GND I/O No. I4 I4 O 28 I1 I1 O1 I1 I4 I5 I1 I2 I1 I3 Description Positive LVDS differentiaI data inputs. Negative LVDS differential data inputs. TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 3 control lines — FPLINE, FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data Enable). Positive LVDS differential clock input. Negative LVDS differential clock input. TTL Ievel clock output. The falling edge acts as data strobe. TTL level input. When asserted (low input) the receiver outputs are low. Power supply pins for TTL outputs. Ground pins for TTL outputs. Power supply for PLL. Ground pin for PLL. Power supply pin for LVDS inputs. Ground pins for LVDS inputs. DS90CF366 Pin Description — 18-Bit FPD Link Receiver Pin Name RxIN+ RxIN− RxOUT RxCLK IN+ RxCLK IN− RxCLK OUT PWR DOWN V CC GND PLL V CC PLL GND LVDS V CC LVDS GND I/O No. I3 I3 O 21 I1 I1 O1 I1 I4 I5 I1 I2 I1 I3 Description Positive LVDS differentiaI data inputs. Negative LVDS differential data inputs. TTL level data outputs. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines — FPLINE, FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data Enable). Positive LVDS differential clock input. Negative LVDS differential clock input. TTL Ievel clock output. The falling edge acts as data strobe. TTL level input. When asserted (low input) the receiver outputs are low. Power supply pins for TTL outputs. Ground pins for TTL outputs. Power supply for PLL. Ground pin for PLL. Power supply pin for LVDS inputs. Ground pins for LVDS inputs. RECEIVER FAILSAFE FEATURE: These receivers have input failsafe bias circuitry to guaran- tee a stable receiver output for floating or terminated re- ceiver inputs. Under these conditions receiver inputs will be in a HIGH state. If a clock signal is present, data outputs will all be HIGH; if the clock input is also floating/terminated, data outputs will remain in the last valid state. A floating/terminated clock input will result in a LOW clock out- put. 11 www.national.com 11 Page

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