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PDF DS90C387 Data sheet ( Hoja de datos )
| Número de pieza | DS90C387 | |
| Descripción | Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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PRELIMINARY
May 2000
DS90C387/DS90CF388
Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA
General Description
The DS90C387/DS90CF388 transmitter/receiver pair is de-
signed to support dual pixel data transmission between Host
and Flat Panel Display up to QXGA resolutions. The trans-
mitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL
data into 8 LVDS (Low Voltage Differential Signalling) data
streams. Control signals (VSYNC, HSYNC, DE and two
user-defined signals) are sent during blanking intervals. At a
maximum dual pixel rate of 112MHz, LVDS data line speed is
672Mbps, providing a total throughput of 5.38Gbps (672
Megabytes per second). Two other modes are also sup-
ported. 24-bit color data (single pixel) can be clocked into the
transmitter at a maximum rate of 170MHz. In this mode, the
transmitter provides single-to-dual pixel conversion, and the
output LVDS clock rate is 85MHz maximum. The third mode
provides inter-operability with FPD-Link devices.
The LDI chipset is improved over prior generations of
FPD-Link devices and offers higher bandwidth support and
longer cable drive with three areas of enhancement. To in-
crease bandwidth, the maximum pixel clock rate is increased
to 112 (170) MHz and 8 serialized LVDS outputs are pro-
vided. Cable drive is enhanced with a user selectable
pre-emphasis feature that provides additional output current
during transitions to counteract cable loading effects. DC
balancing on a cycle-to-cycle basis, is also provided to re-
duce ISI (Inter-Symbol Interference). With pre-emphasis and
DC balancing, a low distortion eye-pattern is provided at the
receiver end of the cable. A cable deskew capability has
been added to deskew long cables of pair-to-pair skew of up
to +/−1 LVDS data bit time. These three enhancements allow
cables 5 to 10+ meters in length to be driven.
This chipset is an ideal means to solve EMI and cable size
problems for high-resolution flat panel applications. It pro-
vides a reliable interface based on LVDS technology that de-
livers the bandwidth needed for high-resolution panels while
maximizing bit times, and keeping clock rates low to reduce
EMI and shielding requirements. For more details, please re-
fer to the “Applications Information” section of this datasheet.
Features
n Complies with OpenLDI specification for digital display
interfaces
n 32.5 to 112/170MHz clock support
n Supports SVGA through QXGA panel resolutions
n Drives long, low cost cables
n Up to 5.38Gbps bandwidth
n Pre-emphasis reduces cable loading effects
n DC balance data transmission provided by transmitter
reduces ISI distortion
n Deskews +/−1 LVDS data bit time of pair-to-pair skew at
receiver inputs; intra-pair skew tolerance of 300ps
n Dual pixel architecture supports interface to GUI and
timing controller; optional single pixel transmitter inputs
support single pixel GUI interface
n Transmitter rejects cycle-to-cycle jitter
n 5V tolerant on data and control input pins
n Programmable transmitter data and control strobe select
(rising or falling edge strobe)
n Backward compatible configuration select with FPD-Link
n Optional second LVDS clock for backward compatibility
w/ FPD-Link
n Support for two additional user-defined control signals in
DC Balanced mode
n Compatible with TIA/EIA - LVDS Standard
Generalized Block Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation DS100073
DS100073-1
www.national.com
1 page  
Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Min Typ Max Units
TCIT
TxCLK IN Transition Time (Figure 5)
DUAL=Gnd or Vcc
1.0
2.0 3.0
ns
DUAL=1/2Vcc
1.0 1.5 1.7 ns
TCIP
TxCLK IN Period (Figure 6)
DUAL=Gnd or Vcc
8.928
T
30.77
ns
DUAL=1/2Vcc
5.88
15.38
ns
TCIH
TxCLK in High Time (Figure 6)
0.35T
0.5T
0.65T
ns
TCIL
TxCLK in Low Time (Figure 6)
0.35T
0.5T
0.65T
ns
TXIT
TxIN Transition Time
1.5 6.0 ns
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Min
LLHT
LVDS Low-to-High Transition Time (Figure 3), PRE = 0.75V
(disabled)
LVDS Low-to-High Transition Time (Figure 3), PRE = Vcc (max)
LHLT
LVDS High-to-Low Transition Time (Figure 3), PRE = 0.75V
(disabled)
LVDS High-to-Low Transition Time (Figure 3), PRE = Vcc (max)
TBIT
Transmitter Output Bit Width
DUAL=Gnd or Vcc
DUAL=1/2Vcc
TCCS
TxOUT Channel to Channel Skew
TSTC
TxIN Setup to TxCLK IN (Figure 6)
2.7
THTC
TxIN Hold to TxCLK IN (Figure 6)
0
TJCC
Transmitter Jitter Cycle-to-cycle (Figures
13, 14) (Note 5), DUAL=Vcc
f = 112 MHz
f = 85 MHz
f = 65 MHz
f = 56 MHz
f = 32.5 MHz
TPLLS Transmitter Phase Lock Loop Set (Figure 8)
TPDD
Transmitter Powerdown Delay (Figure 10)
Typ
0.14
0.11
0.16
0.11
1/7 TCIP
2/7 TCIP
100
85
60
70
100
75
Max
0.7
0.6
0.8
0.7
100
75
80
120
110
10
100
Units
ns
ns
ns
ns
ns
ns
ps
ns
ns
ps
ps
ps
ps
ps
ms
ns
5 www.national.com
5 Page 
AC Timing Diagrams (Continued)
FIGURE 13. TJCC Test Setup - DS90C387
DS100073-27
FIGURE 14. Timing Diagram of the Input Cycle-to-Cycle Clock Jitter
DS100073-28
11 www.national.com
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet DS90C387.PDF ] | |
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