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PDF FAN4803 Data sheet ( Hoja de datos )
| Número de pieza | FAN4803 | |
| Descripción | 8-Pin PFC and PWM Controller Combo | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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www.fairchildsemi.com
FAN4803
8-Pin PFC and PWM Controller Combo
Features
• Internally synchronized PFC and PWM in one 8-pin IC
• Proprietary one-pin voltage error amplifier with advanc
input current shaping technique
• Peak or average current, continuous boost, leading edge
PFC (Input Current Shaping Technology)
• High efficiency trailing-edge current mode PWM
• Low supply currents; start-up: 150µA typ., operating:
2mA typ.
• Synchronized leading and trailing edge modulation
• Reduces ripple current in the storage capacitor between
the PFC and PWM sections
• Overvoltage, UVLO, and brownout protection
• PFC VCCOVP with PFC Soft Start
General Description
The FAN4803 is a space-saving controller for power factor
corrected, switched mode power supplies that offers very
low start-up and operating currents.
Power Factor Correction (PFC) offers the use of smaller, lower
cost bulk capacitors, reduces power line loading and stress on
the switching FETs, and results in a power supply fully compli-
ant to IEC1000-3-2 specifications. The FAN4803 includes
circuits for the implementation of a leading edge, average
current “boost” type PFC and a trailing edge, PWM.
The FAN4803-1’s PFC and PWM operate at the same
frequency, 67kHz. The PFC frequency of the FAN4803-2 is
automatically set at half that of the 134kHz PWM. This
higher frequency allows the user to design with smaller
PWM components while maintaining the optimum operating
frequency for the PFC. An overvoltage comparator shuts
down the PFC section in the event of a sudden decrease in
load. The PFC section also includes peak current limiting for
enhanced system reliability.
Block Diagram
VEAO
4
7V
35µA
+ PFC OFF
COMP
–
–1
M1 M2
M7
M3
R1
7
VCC
17.5V
16.2V
C1
30pF
M4
ISENSE
3
–1V
ONE PIN ERROR AMPLIFIER
+ PFC ILIMIT
– VCC
–4
PFC/PWM UVLO
+
COMP
–
VREF
26k
VDC
5
40k
ILIMIT
6
1.2V
OSCILLATOR
PFC – 67kHz
PWM – 134kHz
DUTY CYCLE
LIMIT
– PWM COMPARATOR
COMP
+
–
COMP
+
M6
1.5V
– DC ILIMIT
+
+ VCC OVP
COMP
–
REF
VREF
GND
2
PFC
CONTROL
LOGIC
SOFT START
PFC OUT
1
LEADING
EDGE PFC
TRAILING
EDGE PWM
PWM
CONTROL
LOGIC
PWM OUT
8
REV. 1.2.3 11/2/04
1 page  
PRODUCT SPECIFICATION
FAN4803
GND
GND is the return point for all circuits associated with
this part. Note: a high-quality, low impedance ground is
critical to the proper operation of the IC. High frequency
grounding techniques should be used.
Power Factor Correction
Power factor correction makes a nonlinear load look like a
resistive load to the AC line. For a resistor, the current drawn
from the line is in phase with, and proportional to, the line
voltage. This is defined as a unity power factor is (one). A
common class of nonlinear load is the input of a most power
supplies, which use a bridge rectifier and capacitive input fil-
ter fed from the line. Peak-charging effect, which occurs on
the input filter capacitor in such a supply, causes brief high-
amplitude pulses of current to flow from the power line,
rather than a sinusoidal current in phase with the line volt-
age. Such a supply presents a power factor to the line of less
than one (another way to state this is that it causes significant
current harmonics to appear at its input). If the input current
drawn by such a supply (or any other nonlinear load) can be
made to follow the input voltage in instantaneous amplitude,
it will appear resistive to the AC line and a unity power factor
will be achieved.
To hold the input current draw of a device drawing power
from the AC line in phase with, and proportional to, the input
voltage, a way must be found to prevent that device from
loading the line except in proportion to the instantaneous line
voltage. The PFC section of the FAN4803 uses a boost-
mode DC-DC converter to accomplish this. The input to the
converter is the full wave rectified AC line voltage. No filter-
ing is applied following the bridge rectifier, so the input
voltage to the boost converter ranges, at twice line frequency,
from zero volts to the peak value of the AC input and back to
zero. By forcing the boost converter to meet two simulta-
neous conditions, it is possible to ensure that the current that
the converter draws from the power line matches the instan-
taneous line voltage. One of these conditions is that the
output voltage of the boost converter must be set higher than
the peak value of the line voltage. A commonly used value is
385VDC, to allow for a high line of 270VACRMS. The other
condition is that the current that the converter is allowed to
draw from the line at any given instant must be proportional
to the line voltage.
Since the boost converter topology in the FAN4803 PFC is
of the current-averaging type, no slope compensation is
required.
Leading/Trailing Modulation
Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will
turn ON right after the trailing edge of the system clock.
The error amplifier output voltage is then compared with the
modulating ramp. When the modulating ramp reaches the
level of the error amplifier output voltage, the switch will be
turned OFF. When the switch is ON, the inductor current will
ramp up. The effective duty cycle of the trailing edge modu-
lation is determined during the ON time of the switch. Figure
2 shows a typical trailing edge control scheme.
L1
I1
+
VIN
DC
SW2 I2 I3
I4
SW1
C1
RL
REF +–EAU3
RAMP
OSC
CLK
U4
+
– U1
DFF
RQ
D U2
Q
CLK
RAMP
VEAO
VSW1
TIME
TIME
Figure 2. Typical Trailing Edge Control Scheme.
REV. 1.2.3 11/2/04
5
5 Page 
PRODUCT SPECIFICATION
Mechanical Dimensions
Package: S08
8 Pin SOIC
0.189 - 0.199
(4.80 - 5.06)
8
PIN 1 ID
0.148 - 0.158 0.228 - 0.244
(3.76 - 4.01) (5.79 - 6.20)
0.017 - 0.027
(0.43 - 0.69)
(4 PLACES)
1
0.050 BSC
(1.27 BSC)
0.059 - 0.069
(1.49 - 1.75)
0°–8°
0.055 - 0.061
(1.40 - 1.55)
0.012 - 0.020
(0.30 - 0.51)
SEATING PLANE
0.004 - 0.010
(0.10 - 0.26)
0.015 - 0.035
(0.38 - 0.89)
0.006 - 0.010
(0.15 - 0.26)
Package: P08
8-Pin PDIP
0.365 - 0.385
(9.27 - 9.77)
0.055 - 0.065
(1.39 - 1.65)
8
PIN 1 ID
0.240 - 0.260 0.299 - 0.335
(6.09 - 6.60) (7.59 - 8.50)
0.020 MIN
(0.51 MIN)
(4 PLACES)
1
0.100 BSC
(2.54 BSC)
0.170 MAX
(4.32 MAX)
0.015 MIN
(0.38 MIN)
0.125 MIN
(3.18 MIN)
0.016 - 0.020
(0.40 - 0.51)
SEATING PLANE
0° - 15°
0.008 - 0.012
(0.20 - 0.31)
FAN4803
REV. 1.2.3 11/2/04
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet FAN4803.PDF ] | |
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