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PDF CXA2108 Data sheet ( Hoja de datos )
| Número de pieza | CXA2108 | |
| Descripción | Constant-Current Driver for Full Color LED Display | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXA2108Q
Constant-Current Driver for Full Color LED Display
For the availability of this product, please contact the sales office.
Description
The CXA2108Q is a 1,024-gradation LED driver
which is ideal for full color LED displays. This IC has
24 outputs and a maximum output current of 60mA.
Time division allows driving of either two or six LEDs
per output by connecting an external FET or other
switch. The luminance (PWM) and drive current for
each LED are set using the internal RAM. The LED
type is common anode.
80 pin QFP (Plastic)
Features
• 24 outputs: 10-bit (1,024-gradation) PWM current outputs
• Maximum output current: 60mA
• LED type: Common anode
• 4-bit brightness function capable of switching the basic PWM pulse width in 16 steps
• Time division allows driving of up to six LEDs with a single output, making it possible to configure a high
definition display with few driver ICs.
• Coarse Adj. (2 bits) and Fine Adj. (8 bits) output current adjustment for each LED makes it possible to drive
R, G and B using the same output from the same IC. In addition, the characteristics variance of each LED
can also be corrected.
• All luminance (PWM) data and drive current data are set by writing to the internal RAM.
• PWM emitting can be performed up to 15 times per frame to realize a screen with little flicker.
• Two built-in PWM data RAM make it possible to set the next luminance data even during PWM operation.
• Abnormal internal temperature detection circuit
• Single 5V power supply
• Surface mounting package (80-pin QFP)
Applications
LED display panels
Structure
Bi-CMOS silicon monolithic IC
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
AVCC, DVCC
• Digital input voltage
VI_D
• Digital output current
Io_D
• Driver output voltage
V_DVR
• Driver output current
• Operating temperature∗1
I_DVR
Topr
• Storage temperature
Tstg
• Allowable power dissipation∗1 (Ta = 65°C or less) PD
–0.3 to +6.0
–0.3 to DVCC + 0.3
–5.0 to +5.0
0 to AVCC + 0.3
–1 to +80
–40 to +80
–65 to +150
1.5
V
V
mA
V
mA
°C
°C
W
Recommended Operating Range
• Supply voltage
• Driver output compliance voltage
• Operating temperature (ambient temperature)∗1
• Operating temperature (case temperature)∗1
AVCC, DVCC
Vcmp
Ta
Tc
4.75 to 5.25
1.5 to AVCC + 0.3
–20 to +65
–20 to +110
V
V
°C
°C
∗1 When mounted on a printed circuit board
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E98333B91-PS
1 page  
Pin
No.
Reference
Symbol I/O voltage
level
47 XCS
I CMOS
50 XR/W I CMOS
48 XWR
I CMOS
49 XRD
I CMOS
46 DLDI
I CMOS
CXA2108Q
Equivalent circuit
DVCC
46 47 48
49 50
DGND
Description
Internal RAM chip select.
Internal RAM access is enabled by
inputting low level. (See Table 1.
Read/Write Switching Condition
Correspondence Table.)
Internal RAM read/write select.
Write mode is selected for high level, and
read mode for low level. See Table 1.
Read/Write Switching Condition
Correspondence Table for the actual
read/write switching signal input conditions.
Write clock input.
This pin is used to input the clock for
writing the luminance, brightness and
drive current data. It is not
synchronized with CLK.
Read clock input.
This pin is used to input the clock for
externally reading the luminance,
brightness and drive current data. It is
not synchronized with CLK.
Trigger signal input for luminance data
RAM (A)/(B) switching and PWM
output start.
(See the Timing Charts.)
–5–
5 Page 
Timing Charts (RAM)
(1) Write mode (XR/W = H)
XWR
A0 to 9
TWR
TCWR
TSWR
THWR
CXA2108Q
D0 to 9
Note) The address is not latched internally, so do not change the address while XWR is low.
(1) Read mode (XR/W = L)
TRD
XRD
TCRD
TSRD
THRD
A0 to 9
TPDD
D0 to 9
Note) The address is not latched internally, so do not change the address while XRD is low.
– 11 –
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet CXA2108.PDF ] | |
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