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PDF CXA2027 Data sheet ( Hoja de datos )
| Número de pieza | CXA2027 | |
| Descripción | Analog signal processor IC | |
| Fabricantes | Sony Corporation | |
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CXA2027Q
Analog signal processor IC
For the availability of this product, please contact the sales office.
Description
The CXA2027Q is an analog signal processor for
48 pin QFP (Plastic)
CCD linear image sensor output signal. This device
is suitable for 3 lines of full-color CCD linear image
sensor (ILX516K/ILX518K/ILX520K: 3648 pixels ×
3 lines/5363 pixels × 3 lines/7078 pixels × 3 lines).
This device has a built-in sample-and-hold, clamp,
multiplex, gain control amplifier circuits and can be
connected directly with external AD converters.
(Sony’s CXD2311AR, CXD1175AM or CXA1977R
are recommended as AD converters.)
Absolute Maximum Ratings
• Supply voltage
VCC
–0.3 to 7
V
Features
• Sample-and-hold circuit
• Pixel-clamp and line-clamp circuit
• Multiplex circuit
• ADC driver circuit
• Input voltage
VI –0.3 to VCC + 0.3 V
• Output voltage
VO –0.3 to VCC + 0.3 V
• Storage temperature Tstg –55 to +150 °C
• Allowable power dissipation
PD 640 mW
• Gain control amplifier circuit
• Offset control circuit
• Clock frequency: 1.5 to 6MHz (after multiplex)
Operating Conditions (Typ. in parentheses)
• Supply voltage
VCC 4.75 to 5.25 (5.0) V
• Digital input voltage High VIH 3.5 to VCC (VCC) V
Applications
Color image scanner
• Digital input voltage Low VIL 0 to 0.8 (0) V
• Operating temperature Topr 0 to +70 °C
Structure
Bipolar silicon monolithic IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95210A78
1 page  
CXA2027Q
Pin Symbol
No. (I/O)
Typical pin voltage
DC AC
Equivalent circuit
Description
VCCA
20
SIGOUT
(O)
21 VCCP 5V
22 GC (I) 0 to 5V
2.0V
+MAX1.8V
(2.0 to 3.8V)
VCCA
21
100µ
1k
20
2mA
VCCA
VCCA VCCA
20k
129 4k
22
100µ
30k 1.5k
Signal output pin
(to AD converter)
Power supply pin
(for signal output system)
Voltage input pin for post-
stage GCA gain adjustment
(Can be open; in that case
outputs 3V)
Lo: 0 to 0.8V
Hi: 3.5 to 5V
23 LCLP (I)
Lo:
clamp OFF
Hi:
clamp ON
24 TD4 (O) 1.7 to 3.6V
25 TD6 (O) 2.0 to 3.6V
26 TD5 (O)
27 TD1 (O)
1.7 to 3.6V
28 TD2 (O)
29 TD3 (O)
Lo: 0 to 0.8V
Hi: 3.5 to 5V
30 CLP (I)
Lo:
clamp OFF
Hi:
clamp ON
31 MPX1 (I)
Lo: 0 to 0.8V
Hi: 3.5 to 5V
VCCA
23
129
VCCA
100µ
1.5V
2k
VCCA VCCA
24
129
126µ
VCCA
VCCA
129
30
250µ
1.5V
1k
VCCA
VCCA
1.5k
31
129
1.2V
100µ
Line clamp pulse input pin
(Apply high level during the
optical black period of CCD
output)
DA4 analog output test pin
DA6 analog output test pin
DA5 analog output test pin
DA1 analog output test pin
DA2 analog output test pin
DA3 analog output test pin
Pixel clamp pulse input pin
(Apply high level during the
precharge period of CCD
output)
MPX channel switching
pulse input pin 1
(See high/low table under
Pin 32 in following section.)
–5–
5 Page 
CXA2027Q
Pulse Timing
[Pulse Timing 1 (pixel units)]
CLP pulse and SH pulse
Input the SH pulse at the end of the effective signal so as not to be affected by signal fluctuation caused by
the clamp.
SH pulse and MPX pulse (MPX1, MPX2)
Input the SH pulse in sync with the reference channel.
MPX1 pulse and MPX2 pulse
Delay the timing of MPX2 when G changes to B. (Table 1, t3)
CCD signal
(R-IN/
G-IN/
B-IN)
Reset level
Precharge level
CLP
t2
SH 50%
t4
t1
50%
Effective signal level
MPX1
MPX2
50%
t3
50%
tr = tf = 5ns
SIGOUT
Data taken in at
AD converter
t5
Output channel B R G B R
Min. Typ. Max.
t1 100ns
t2
40ns
50ns
t3 5ns 20ns
t4 5ns
t5 60ns
Table 1
– 11 –
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet CXA2027.PDF ] | |
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