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PDF LTC3733 Data sheet ( Hoja de datos )
| Número de pieza | LTC3733 | |
| Descripción | 3-Phase/ Buck Controllers for AMD CPUs | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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LTC3733/LTC3733-1
3-Phase, Buck
Controllers for AMD CPUs
FEATURES
s 3-Phase Controller with Onboard MOSFET Drivers
s Current Mode Control Ensures Current Sharing
s Differential Amplifier Accurately Senses VOUT
s ±5% Output Current Matching Optimizes Thermal
Performance and Size of Inductors and MOSFETs
s Reduced Input and Output Capacitance
s Supports Active Voltage Positioning
s VID Programmable Output Voltage from 0.8V to 1.55V
(AMD OpteronTM CPU)
s 6-Phase, 90A to 120A Operation
s Output Power Good Indicator with Adaptive Blanking
s 210kHz to 530kHz Per Phase, PLL, Fixed Frequency
s Synchronizable (LTC3733-1)
s PWM, Stage Shedding or Burst Mode® Operation
s OPTI-LOOP® Compensation Minimizes COUT
s Adjustable Soft-Start Current Ramping
s Short-Circuit Shutdown Timer with Defeat Option
s No_CPU Detection
s 36-Lead 0.209" SSOP and 38-Lead (5mm × 7mm) QFN
U
APPLICATIO S
s High Performance Notebook Computers
s Servers, Desktop Computers and Workstations
DESCRIPTIO
The LTC®3733 family are PolyPhase® synchronous step-
down switching regulator controllers that drive all
N-channel external power MOSFET stages in a phase-
lockable, fixed frequency architecture. The 3-phase con-
troller drives its output stages with 120° phase separation
at frequencies of up to 530kHz per phase to minimize the
RMS current dissipated by the ESR of both the input and
output filter capacitors. The 3-phase technique effectively
triples the fundamental frequency, improving transient
response while operating each phase at an optimal fre-
quency for efficiency and ease of thermal design. Light
load efficiency is optimized by using a choice of output
stage shedding or Burst Mode technology.
A differential amplifier provides true remote sensing of both
the high and low sides of the output voltage at load points.
Soft-start and a defeatable, timed short-circuit shutdown
protect the MOSFETs and the load. A foldback current
circuit also provides protection for the external MOSFETs
under short-circuit or overload conditions. An all-“1” VID
detector turns off the regulator after 1µs timeout.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode, OPTI-LOOP and PolyPhase are registered trademarks of Linear Technology
Corporation. AMD Opteron is a trademark of Advanced Micro Devices, Inc.
TYPICAL APPLICATIO
5V
10µF
0.1µF
SW3 SW2 SW1
POWER GOOD INDICATOR
OPTIONAL SYN IN
5 VID BITS
ON/OFF
680pF
5k
0.1µF
100pF
VCC TG1
LTC3733-1 SW1
BOOST1
BOOST2
BG1
BOOST3
SENSE1+
SENSE1–
PGOOD
PLLIN
PLLFLTR
VID0-VID4
RUN
ITH
SS
SGND
EAIN
IN–
IN+
TG2
SW2
BG2
PGND
SENSE2+
SENSE2–
TG3
SW3
BG3
SENSE3+
SENSE3–
L1 0.8µH
D1
0.002Ω
VIN
+
5V TO 28V
22µF
35V
×2
VIN
L2 0.8µH
0.002Ω
D2
VOUT
0.8V TO 1.55V
65A
VIN
L3 0.8µH
0.002Ω
D3
+
COUT
470µF
4V
×4
3733 F01
Figure 1. High Current Triple Phase Step-Down Converter
3733f
1
1 page  
TYPICAL PERFOR A CE CHARACTERISTICS
LTC3733/LTC3733-1
Efficiency vs IOUT
100
90 VFCB = OPEN
80
70
60
VFCB = 5V
50
40 VFCB = 0V
30
20
10
0
0.1
VIN = 8V
VOUT = 1.5V
1 10
INDUCTOR CURRENT (A)
100
3733 G01
Reference Voltage vs
Temperature
610
Efficiency vs VIN
100
VOUT = 1.5V
f = 210kHz
95 IL = 20A
90
IL = 50A
85
80
75
70
0
5 10 15
VIN (V)
Error Amplifier gm vs
Temperature
4.0
20 25
3733 G02
605 3.5
600 3.0
595 2.5
590
–45 –30 –15 0 15 30 45 60 75 90
TEMPERATURE (°C)
3733 G04
Oscillator Frequency vs
Temperature
600
550
500 VPLLFLTR = 2.4V
450 VPLLFLTR = 5V
400
350
VPLLFLTR = 1.2V
300
250
200
VPLLFLTR = 0V
150
100
–45 –30 –15 0 15 30 45 60 75 90
TEMPERATURE (°C)
3733 G07
2.0
–45 –30 –15 0 15 30 45 60 75 90
TEMPERATURE (°C)
3733 G05
Oscillator Frequency vs VPLLFLTR
550
500
450
400
350
300
250
200
0
0.4 0.8 1.2 1.6 2.0 2.4
VPLLFLTR (V)
3733 G08
Efficiency vs Frequency
100
VOUT = 1.5V
ILOAD = 20A
97
VIN = 8V
94
VIN = 5V
91
VIN = 12V
88
VIN = 20V
85
200 250 300 350 400 450 500 550
FREQUENCY (kHz)
3733 G03
Maximum ISENSE Threshold vs
Temperature
85
80
VO = 1.55V
75
VO = 0.8V
70
65
–45 –30 –15 0 15 30 45 60 75 90
TEMPERATURE (°C)
3733 G06
Undervoltage Reset Voltage vs
Temperature
5.0
4.5
4.0
3.5
3.0
–45 –30 –15 0 15 30 45 60 75 90
TEMPERATURE (°C)
3733 G09
3733f
5
5 Page 
U
OPERATIO (Refer to Functional Diagram)
Main Control Loop
The IC uses a constant frequency, current mode step-
down architecture. During normal operation, each top
MOSFET is turned on each cycle when the oscillator sets
the RS latch, and turned off when the main current
comparator, I1, resets each RS latch. The peak inductor
current at which I1 resets the RS latch is controlled by the
voltage on the ITH pin, which is the output of the error
amplifier EA. The EAIN pin receives a portion of the voltage
feedback signal via the DIFFOUT pin through the internal
VID DAC and is compared to the internal reference voltage.
When the load current increases, it causes a slight de-
crease in the EAIN pin voltage relative to the 0.6V refer-
ence, which in turn causes the ITH voltage to increase until
each inductor’s average current matches one third of the
new load current (assuming all three current sensing
resistors are equal). In Burst Mode operation and stage
shedding mode, after each top MOSFET has turned off, the
bottom MOSFET is turned on until either the inductor
current starts to reverse, as indicated by current compara-
tor I2, or the beginning of the next cycle.
The top MOSFET drivers are biased from floating boot-
strap capacitor CB, which is normally recharged during
each off cycle through an external Schottky diode. When
VIN decreases to a voltage close to VOUT, however, the
loop may enter dropout and attempt to turn on the top
MOSFET continuously. The dropout detector counts the
number of oscillator cycles that the bottom MOSFET
remains off and periodically forces a brief on period to
allow CB to recharge.
The main control loop is shut down by pulling the RUN pin
low. Releasing RUN allows an internal 1.5µA current
source to charge soft-start capacitor CSS at the SS pin. The
internal ITH voltage is then clamped to the SS voltage when
CSS is slowly charged up. This “soft-start” clamping
prevents abrupt current from being drawn from the input
power source. When the RUN pin is low, all functions are
kept in a controlled state.
Low Current Operation
The FCB pin is a multifunction pin: 1) an analog compara-
tor input to provide regulation for a secondary winding by
LTC3733/LTC3733-1
forcing temporary forced PWM operation and 2) a logic
input to select between three modes of operation.
When the FCB pin voltage is below 0.6V, the controller
performs as a continuous, PWM current mode synchro-
nous switching regulator. The top and bottom MOSFETs
are alternately turned on to maintain the output voltage
independent of direction of inductor current. When the
FCB pin is below VCC –␣ 1V but greater than 0.6V, the
controller performs as a Burst Mode switching regulator.
Burst Mode operation sets a minimum output current level
before turning off the top switch and turns off the synchro-
nous MOSFET(s) when the inductor current goes nega-
tive. This combination of requirements will, at low current,
force the ITH pin below a voltage threshold that will
temporarily shut off both output MOSFETs until the output
voltage drops slightly. There is a burst comparator having
60mV of hysteresis tied to the ITH pin. This hysteresis
results in output signals to the MOSFETs that turn them on
for several cycles, followed by a variable “sleep” interval
depending upon the load current. The resultant output
voltage ripple is held to a very small value by having the
hysteretic comparator after the error amplifier gain block.
When the FCB pin is tied to the VCC pin, Burst Mode
operation is disabled and the forced minimum inductor
current requirement is removed. This provides constant
frequency, discontinuous current operation over the wid-
est possible output current range. At approximately 10%
of maximum designed load current, the second and third
output stages are shut off and the first controller alone is
active in discontinuous current mode. This “stage shed-
ding” optimizes efficiency by eliminating the gate charging
losses and switching losses of the other two output
stages. Additional cycles will be skipped when the output
load current drops below 1% of maximum designed load
current in order to maintain the output voltage. This
constant frequency operation is not as efficient as Burst
Mode operation at very light loads, but does provide lower
noise, constant frequency operating mode down to very
light load conditions.
Tying the FCB pin to ground will force continuous current
operation. This is the least efficient operating mode, but
may be desirable in certain applications. The output can
3733f
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LTC3733.PDF ] | |
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