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PDF LTC1873 Data sheet ( Hoja de datos )
| Número de pieza | LTC1873 | |
| Descripción | Dual 550kHz Synchronous 2-Phase Switching Regulator Controller with 5-Bit VID | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LTC1873 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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LTC1873
Dual 550kHz Synchronous
2-Phase Switching Regulator
Controller with 5-Bit VID
FEATURES
s Two Independent PWM Controllers in One Package
s Side 1 Output Is Compliant with Intel Desktop
VRM 8.4 Specifications (Includes 5-Bit VID DAC)
s 1.3V to 3.5V Output Voltage with 50mV/100mV Steps
s Two Sides Run Out-of-Phase to Minimize CIN
s All N-Channel External MOSFET Architecture
s No External Current Sense Resistors Required
s Precison Internal 0.8V ±1% Reference
s 550kHz Switching Frequency Minimizes External
Component Size
s Very Fast Transient Response
s Up to 25A Output Current per Channel
s Low Shutdown Current: < 100µA
s Small 28-Pin SSOP Package
U
APPLICATIO S
s Microprocessor Core and I/O Supplies
s Multiple Logic Supply Generator
s High Efficiency Power Conversion
s Chipset Power Supply
DESCRIPTIO
The LTC®1873 is a dual switching regulator controller opti-
mized for high efficiency with low input voltages. It includes
two complete, on-chip, independent switching regulator con-
trollers. Each is designed to drive a pair of external
N-channel MOSFETs in a voltage mode feedback, synchro-
nous buck configuration. The LTC1873 includes digital out-
put voltage adjustment on side 1 that conforms to the Intel
Desktop VID specification. A constant-frequency, true PWM
design minimizes external component size and cost and
optimizes load transient performance. The synchronous buck
architecture automatically shifts to discontinuous and then to
Burst ModeTM operation as the output load decreases, ensur-
ing maximum efficiency over a wide range of load currents.
The LTC1873 features an onboard reference trimmed to 1%
and delivers better than 1.5% regulation at the converter
outputs over all combinations of line, load and temperature.
Each channel can be enabled independently; with both chan-
nels disabled, the LTC1873 shuts down and supply current
drops below 100µA.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a trademark of Linear Technology Corporation.
TYPICAL APPLICATIO
Low Cost Desktop CPU Supply with RDRAM Keepalive
4.5V TO 5.5V
STBY/ON
10k
0.1%
1k
1k
4.75k +
0.1%
330pF
68k
QSS1
QSS2
+
10Ω CIN
10µF
VCC
PVCC
FB2
56pF
COMP2
BOOST2
TG2
SW2
RUN/SS2
RUN/SS1
0.1µF
BG2
IMAX2
LTC1873 FAULT
SENSE
BOOST1
47k
220pF
56k
5-BIT VID
FB1
39pF
COMP1
FCB
VID4:0
SGND
TG1
SW1
BG1
IMAX1
PGND
33k
MBR0530T
IN OUT
1µF LT1761
GND ADJ
QT2 1µF
L2
QB2
MBR0530T
QT1B
QT1A
1µF
L1
QB1B
QB1A
16.2k
0.1%
16.9k
0.1%
+
VRDRAM
2.5V/7A
2.45V/100mA STANDBY
COUT2
+
1873 TA01
VCORE
1.3V TO 3.5V
20A
COUT1
CIN = SANYO 10MV1200GX (6 IN PARALLEL)
COUT1 = SANYO 6MV1500GX (8 IN PARALLEL)
COUT2 = SANYO 6MV1500GX (3 IN PARALLEL)
L1: 1µH SUMIDA CEP125-1R0MC-H
L2: 2.2µH COILTRONICS UP2B-2R2
QSS1, QSS2: MOTOROLA MMBT3904LT1
QT1A, QT1B, QB1A, QB1B: FAIRCHILD FDS6670A
QT2, QB2: 1/2 SILICONIX Si4966
1
1 page  
LTC1873
PI FU CTIO S
PVCC (Pin 1): Driver Power Supply Input. PVCC provides
power to the two BGn output drivers. PVCC must be
connected to a voltage high enough to fully turn on the
external MOSFETs QB1 and QB2. PVCC should generally
be connected directly to VIN. PVCC requires at least a 1µF
bypass capacitor directly to PGND.
BOOST1 (Pin 2): Controller 1 Top Gate Driver Supply. The
BOOST1 pin supplies power to the floating TG1 driver.
BOOST1 should be bypassed to SW1 with a 1µF capacitor.
An additional Schottky diode from VIN to BOOST1 pin will
create a complete floating charge-pumped supply at
BOOST1. No other external supplies are required.
BG1 (Pin 3): Controller 1 Bottom Gate Drive. The BG1 pin
drives the gate of the bottom N-channel synchronous
switch MOSFET, QB1. BG1 is designed to drive up to
10,000pF of gate capacitance directly. If RUN/SS1 goes
low, BG1 will go low, turning off QB1. If FAULT mode is
tripped, BG1 will go high and stay high, keeping QB1 on
until the power is cycled.
TG1 (Pin 4): Controller 1 Top Gate Drive. The TG1 pin
drives the gate of the top N-channel MOSFET, QT1. The
TG1 driver draws power from the BOOST1 pin and returns
to the SW1 pin, providing true floating drive to QT1. TG1
is designed to drive up to 10,000pF of gate capacitance
directly. In shutdown or fault modes, TG1 will go low.
SW1 (Pin 5): Controller 1 Switching Node. SW1 should be
connected to the switching node of converter 1. The TG1
driver ground returns to SW1, providing floating gate
drive to the top N-channel MOSFET switch, QT1. The
voltage at SW1 is compared to IMAX1 by the current limit
comparator while the bottom MOSFET, QB1, is on.
IMAX1 (Pin 6): Controller 1 Current Limit Set. The IMAX1
pin sets the current limit comparator threshold for
controller 1. If the voltage drop across the bottom MOSFET,
QB1, exceeds the magnitude of the voltage at IMAX1,
controller 1 will go into current limit. The IMAX1 pin has an
internal 10µA current source pull-up, allowing the current
threshold to be set with a single external resistor to PGND.
This current setting resistor should be Kelvin connected to
the source of QB1. See the Current Limit Programming
section for more information on choosing RIMAX.
FCB (Pin 7): Force Continuous Bar. The FCB pin forces
both converters to maintain continuous synchronous
operation regardless of load when the voltage at FCB
drops below 0.8V. FCB is normally tied to VCC. To force
continuous operation, tie FCB to SGND. FCB can also be
connected to a feedback resistor divider from a secondary
winding on one converter’s inductor to generate a third
regulated output voltage. Do not leave FCB floating.
RUN/SS1 (Pin 8): Controller 1 Run/Soft-Start. Pulling
RUN/SS1 to SGND will disable controller 1 and turn off
both of its external MOSFET switches. Pulling both
RUN/SS pins down will shut down the entire LTC1873,
dropping the quiescent supply current below 50µA. A
capacitor from RUN/SS1 to SGND will control the turn-on
time and rate of rise of the controller 1 output voltage at
power-up. An internal 3.5µA current source pull-up at
RUN/SS1 pin sets the turn-on time at approximately
50ms/µF.
COMP1 (Pin 9): Controller 1 Loop Compensation. The
COMP1 pin is connected directly to the output of the first
controller’s error amplifier and the input to the PWM
comparator. An RC network is used at the COMP1 pin to
compensate the feedback loop for optimum transient
response.
SGND (Pin 10): Signal Ground. All internal low power
circuitry returns to the SGND pin. Connect to a low
impedance ground, separated from the PGND node. All
feedback, compensation and soft-start connections should
return to SGND. SGND and PGND should connect only at
a single point, near the PGND pin and the negative plate of
the CIN bypass capacitor.
FB1 (Pin 11): Controller 1 Feedback Input. The loop
compensation network for controller 1 should be con-
nected to FB1. FB1 is connected internally to the VID
resistor network to set the output voltage at side 1.
SENSE (Pin 12): Output Sense. Connect to VOUT1.
VID0 to VID4 (Pins 13 to 17): VID Programming Inputs.
These are logic inputs that set the output voltage at side 1
to a preprogrammed value (see Table 1). VID4 is the MSB,
VID0 is the LSB. The codes selected by the VIDn inputs
correspond to the Intel Desktop VID specification. Each
5
5 Page 
LTC1873
APPLICATIO S I FOR ATIO
pin. The output is connected to COMP, which is in turn
connected to the soft-start circuitry and from there to the
PWM generator.
Unlike many regulators that use a resistor divider con-
nected to a high impedance feedback input, the LTC1873
is designed to use an inverting summing amplifier topol-
ogy with the FB pin configured as a virtual ground. This
allows flexibility in choosing pole and zero locations not
available with simple gm configurations. In particular, it
allows the use of “type 3” compensation, which provides
a phase boost at the LC pole frequency and significantly
improves loop phase margin (see Figure 3). The Feedback
Loop/Compensation section contains a detailed explana-
tion of type 3 feedback loops. Note that side 1 of the
LTC1873 includes R1 and RB internally as part of the VID
DAC circuitry.
COMP
R2
+
FB
–
0.8V
FB
C2
C1
C3
R3
R1
RB
1873 F03
VOUT
Figure 3. “Type 3” Feedback Loop (Side 2 Shown)
MIN/MAX COMPARATORS
Two additional feedback loops keep an eye on the primary
feedback amplifier and step in if the feedback node moves
±5% from its nominal 800mV value. The MAX comparator
(see Block Diagram) activates whenever FB rises more
than 5% above 800mV. It immediately turns the top
MOSFET (QT) off and the bottom MOSFET (QB) on and
keeps them that way until FB falls back within 5% of its
nominal value. This pulls the output down as fast as
possible, preventing damage to the (often expensive)
load. If FB rises because the output is shorted to a higher
supply, QB will stay on until the short goes away, the
higher supply current limits or QB dies trying to save the
load. This behavior provides maximum protection against
overvoltage faults at the output, while allowing the circuit
to resume normal operation when the fault is removed.
The overvoltage protection circuit can optionally be set to
latch the output off permanently (see the Overvoltage Fault
section).
The MIN comparator (see Block Diagram) trips whenever
FB is more than 5% below 800mV and immediately forces
the switch duty cycle to 90% to bring the output voltage
back into range. It releases when FB is within the 5%
window. MIN is disabled when the soft-start or current
limit circuits are active—the only two times that the
output should legitimately be below its regulated value.
Notice that the FB pin is the virtual ground node of the
feedback amplifier. A typical compensation network does
not include local DC feedback around the amplifier, so that
the DC level at FB will be an accurate replica of the output
voltage, divided down by R1 and RB (Figure 3). However,
the compensation capacitors will tend to attenuate AC
signals at FB, especially with low bandwidth type 1 feed-
back loops. This creates a situation where the MIN and
MAX comparators do not respond immediately to shifts in
the output voltage, since they monitor the output at FB.
Maximizing feedback loop bandwidth will minimize these
delays and allow MIN and MAX to operate properly. See
the Feedback Loop/Compensation section.
SHUTDOWN/SOFT-START
Each half of the LTC1873 has a RUN/SS pin. The RUN/SS
pins perform two functions: when pulled to ground, each
shuts down its half of the LTC1873, and each acts as a
conventional soft-start pin, enforcing a maximum duty
cycle limit proportional to the voltage at RUN/SS. An
internal 3.5µA current source pull-up is connected to each
RUN/SS pin, allowing a soft-start ramp to be generated
with a single external capacitor to ground. The 3.5µA
current sources are active even when the LTC1873 is shut
down, ensuring the device will start when any external
pull-down at RUN/SS is released. Either side can be shut
down without affecting the operation of the other side. If
both sides are shut down at the same time, the LTC1873
goes into a micropower sleep mode, and quiescent cur-
rent drops typically below 50µA. Entering sleep mode also
resets the FAULT latch, if it was set.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LTC1873.PDF ] | |
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