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PDF CS51313 Data sheet ( Hoja de datos )
| Número de pieza | CS51313 | |
| Descripción | Synchronous CPU Buck Controller Capable of Implementing Multiple Linear Regulators | |
| Fabricantes | Cherry Semiconductor Corporation | |
| Logotipo |  |
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CS51313
Synchronous CPU Buck Controller
Capable of Implementing Multiple Linear Regulators
Description
Features
The CS51313 is a synchronous dual
NFET Buck Regulator Controller. It is
designed to power the core logic of the
latest high performance CPUs. It uses the
V2TM control method to achieve the
fastest possible transient response and
best overall regulation. It incorporates
many additional features required to
ensure the proper operation and protec-
tion of the CPU and Power system. The
CS51313 provides the industry’s most
highly integrated solution, minimizing
external component count, total solution
size, and cost.
The CS51313 is specifically designed to
power Intel’s Pentium® II processor and
includes the following features: 5-bit
DAC with 1.2% tolerance, Power-Good
output, overcurrent hiccup mode protec-
tion, over voltage protection, VCC moni-
tor, Soft Start, adaptive voltage position-
ing and adaptive FET non-overlap time.
A precision reference trimmed to 1% is
also externally available for use by other
regulators. The CS51313 will operate
over an 8.4V to 14V range and is avail-
able in 16 lead narrow body surface
mount package.
Application Diagram
+12V
+3.3V +3.3V
+5V
1200µF/10V
1200µF/10V
1µF
1200µF/10V
x3
VID0
VID1
VID2
VID3
VID4
OVP
VREF
VCC
GND
GATEH
GATEL
VFB
VOUT
PWRGD
COMP
COFF
0.1
µF
680pF
+12 0.01
18K
1%
µF
1µF
3+ 1
IRL3103S
2 - LM358A
51K
1%
100K 1%
22.1K
1%
LM358A
5+
6-
100K
1%
7
102K
1%
FS70VSJ-03
FS70VSJ-03
1.2µH 3.3mΩ
0.1µF
10K
100Ω
510Ω
510Ω
1200µF/ 10V
x2
TIP 31
47µF
VCORE
2.0V@19A
1200µF/10V
x5
PWRGD
VGTL+
1.5V@3A
VCLOCK
2.5V@1A
s Synchronous Switching
Regulator Controller for CPU
VCORE
s Dual N-Channel MOSFET
Synchronous Buck Design
s V2TM Control Topology
s 200ns Transient Loop Response
s 5-bit DAC with 1.2% Tolerance
s Hiccup Mode Overcurrent
Protection
s 40ns Gate Rise and Fall Times
(3.3nF load)
s 65ns Adaptive FET Non-overlap
Time
s Adaptive Voltage Positioning
s Power-Good Output Monitors
Regulator Output
s VCC Monitor Provides Under
Voltage Lockout
s OVP Output Monitors Regulator
Output
s Enable Through use of the
COMP pin
s +1.23V Reference Voltage
Available Externally
Package Options
16 Lead SO Narrow
VID0 1
VID1
VID2
VID3
VREF
VID4
VFB
VOUT
COMP
COFF
PWRGD
OVP
GATE(L)
Gnd
GATE(H)
VCC
V2 is a trademark of Switch Power, Inc.
Pentium is a registered trademark of Intel Corporation.
Rev. 3/11/99
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: [email protected]
Web Site: www.cherry-semi.com
1 A ® Company
1 page  
Electrical Characteristics: 0˚C < TA < 70˚C; 0˚C < TJ < 125˚C; 9V < VCC < 14V;
2.0V DAC Code (VID4 = VID3 =VID2 = VID1 = 0, VID0 = 1), CGATE(H) = CGATE(L) = 3.3nF, COFF = 390pF; Unless otherwise stated.
PARAMETER
TEST CONDITIONS
s General Electrical Specifications
VCC Monitor Start Threshold
VCC Monitor Stop Threshold
Hysteresis
Start - Stop
VCC Supply Current
No Load on GATE(H), GATE(L)
MIN
7.9
7.6
0.15
TYP
8.4
8.1
0.30
12
MAX
UNIT
8.9 V
8.6 V
0.60 V
20 mA
Note 1: All pins are rated 2kV except for the VREF pin (Pin 5) which is typically rated at 800V.
Note 2: The IC power dissipation in a typical application with VCC = 12V, switching frequency fSW = 250kHz, 50nc
MOSFETs and RθJA = 115°C/W yields an operating junction temperature rise of approximately 52°C, and a junction tem-
perature of 77°C with an ambient temperature of 25°C.
Note 3: Guaranteed by design, not 100% tested in production.
Block Diagram
VOUT
VREF
VID0
VID1
VID2
VID3
VID4
VFB
1.10V
-
COMP
EA
PWM COMP
+
-
CURRENT LIMIT
86mV
-
+
-
BANDGAP
REFERENCE
DISCHARGE
COMP
R
+- 0.25V
Q
FAULT
LATCH
S
COFF
OFF
TIME
DAC
UVLO
VCC
GATE(H)
NONOVERLAP
+ LOGIC
-
+
-
VCC
OVP
PWRGD
5
Gnd
GATE(L)
5 Page 
Application Information: continued
The CPU VCC(CORE) tolerance can be affected by any or all
of the following reasons:
1) buck regulator output voltage setpoint accuracy;
2) output voltage change due to discharging or charging of
the bulk decoupling capacitors during a load current tran-
sient;
3) output voltage change due to the ESR and ESL of the
bulk and high frequency decoupling capacitors, circuit
traces, and vias;
4) output voltage ripple and noise.
Budgeting the tolerance is left up to the designer who must
take into account all of the above effects and provide a
VCC(CORE) that will meet the specified tolerance at the
CPU’s inputs.
The designer must also ensure that the regulator compo-
nent junction temperatures are kept within the manufac-
turer’s specified ratings at full load and maximum ambient
temperature. As computer motherboards become increas-
ingly complex, regulator size also becomes important, as
there is less space available for the CPU power supply.
Step 2: Selection of the Output Capacitors
These components must be selected and placed carefully to
yield optimal results. Capacitors should be chosen to pro-
vide acceptable ripple on the regulator output voltage. Key
specifications for output capacitors are their ESR
(Equivalent Series Resistance), and ESL (Equivalent Series
Inductance). For best transient response, a combination of
low value/high frequency and bulk capacitors placed close
to the load will be required.
In order to determine the number of output capacitors the
maximum voltage transient allowed during load transi-
tions has to be specified. The output capacitors must hold
the output voltage within these limits since the inductor
current can not change with the required slew rate. The
output capacitors must therefore have a very low ESL and
ESR.
The voltage change during the load current transient is:
( )∆VOUT = ∆IOUT ×
ESL
∆t
+ ESR +
tTR
COUT
,
where
∆IOUT / ∆t = load current slew rate;
∆IOUT = load transient;
∆t = load transient duration time;
ESL = Maximum allowable ESL including capacitors,
circuit traces, and vias;
ESR = Maximum allowable ESR including capacitors
and circuit traces;
tTR = output voltage transient response time.
The designer has to independently assign values for the
change in output voltage due to ESR, ESL, and output
capacitor discharging or charging. Empirical data indicates
that most of the output voltage change (droop or spike
depending on the load current transition) results from the
total output capacitor ESR.
The maximum allowable ESR can then be determined
according to the formula
ESRMAX =
∆VESR
∆IOUT
,
where ∆VESR = change in output voltage due to ESR
(assigned by the designer).
Once the maximum allowable ESR is determined, the
number of output capacitors can be found by using the for-
mula
Number of capacitors =
ESRCAP
ESRMAX
,
where
ESRCAP = maximum ESR per capacitor (specified in
manufacturer’s data sheet);
ESRMAX = maximum allowable ESR.
The actual output voltage deviation due to ESR can then be
verified and compared to the value assigned by the design-
er:
∆VESR = ∆IOUT × ESRMAX
Similarly, the maximum allowable ESL is calculated from
the following formula:
ESLMAX =
∆VESL × ∆t
∆I
,
where
∆I/∆T = load current slew rate (as high as 20A/µs);
∆VESL = change in output voltage due to ESL.
The actual maximum allowable ESL can be determined by
using the equation:
ESLMAX =
ESLCAP
Number of output capacitors
,
where ESLCAP = maximum ESL per capacitor (it is estimat-
ed that a 10 × 12mm Aluminum Electrolytic capacitor has
approximately 4nH of package inductance).
The actual output voltage deviation due to the actual maxi-
mum ESL can then be verified:
∆VESL =
ESLMAX × ∆I
∆t
.
The designer now must determine the change in output
voltage due to output capacitor discharge during the tran-
sient:
∆VCAP =
∆I × ∆tTR
COUT
,
where
∆tTR = the output voltage transient response time
(assigned by the designer);
∆VCAP = output voltage deviation due to output capaci-
tor discharge;
∆I = Load step.
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet CS51313.PDF ] | |
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