|
|
PDF AD569 Data sheet ( Hoja de datos )
| Número de pieza | AD569 | |
| Descripción | 16-Bit Monotonic Voltage Output D/A Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD569 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
|
No Preview Available !
a
FEATURES
Guaranteed 16-Bit Monotonicity
Monolithic BiMOS II Construction
؎0.01% Typical Nonlinearity
8- and 16-Bit Bus Compatibility
3 s Settling to 16 Bits
Low Drift
Low Power
Low Noise
APPLICATIONS
Robotics
Closed-Loop Positioning
High-Resolution ADCs
Microprocessor-Based Process Control
MIL-STD-883 Compliant Versions Available
16-Bit Monotonic
Voltage Output D/A Converter
AD569
FUNCTIONAL BLOCK DIAGRAM
PRODUCT DESCRIPTION
The AD569 is a monolithic 16-bit digital-to-analog converter
(DAC) manufactured in Analog Devices’ BiMOS II process.
BiMOS II allows the fabrication of low power CMOS logic
functions on the same chip as high precision bipolar linear cir-
cuitry. The AD569 chip includes two resistor strings, selector
switches decoding logic, buffer amplifiers, and double-buffered
input latches.
The AD569’s voltage-segmented architecture insures 16-bit
monotonicity over time and temperature. Integral nonlinearity is
maintained at ± 0.01%, while differential nonlinearity is
± 0.0004%. The on-chip, high-speed buffer amplifiers provide a
voltage output settling time of 3 µs to within ± 0.001% for a
full-scale step.
The reference input voltage which determines the output range
can be either unipolar or bipolar. Nominal reference range is
± 5 V and separate reference force and sense connections are
provided for high accuracy applications. The AD569 can oper-
ate with an ac reference in multiplying applications.
Data may be loaded into the AD569’s input latches from 8- and
16-bit buses. The double-buffered structure simplifies 8-bit bus
interfacing and allows multiple DACs to be loaded asynchro-
nously and updated simultaneously. Four TTL/LSTTL/5 V
CMOS-compatible signals control the latches: CS, LBE, HBE,
and LDAC
The AD569 is available in five grades: J and K versions are
specified from 0°C to +70°C and are packaged in a 28-pin plas-
tic DIP and 28-pin PLCC package; AD and BD versions are
specified from –25°C to +85°C and are packaged in a 28-pin
ceramic DIP. The SD version, also in a 28-pin ceramic DIP, is
specified from –55°C to +125°C.
PRODUCT HIGHLIGHTS
1. Monotonicity to 16 bits is insured by the AD569’s voltage-
segmented architecture.
2. The output range is ratiometric to an external reference or ac
signal. Gain error and gain drift of the AD569 are negligible.
3. The AD569’s versatile data input structure allows loading
from 8- and 16-bit buses.
4. The on-chip output buffer amplifier can supply ± 5 V into a
1 kΩ load, and can drive capacitive loads of up to 1000 pF.
5. Kelvin connections to the reference inputs preserve the gain
and offset accuracy of the transfer function in the presence of
wiring resistances and ground currents.
6. The AD569 is available in versions compliant with MIL-STD-
883. Refer to the Analog Devices Military Products Data-
book or current AD569/883B data sheet for detailed
specifications.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
AD569
FUNCTIONAL DESCRIPTION
The AD569 consists of two resistor strings, each of which is di-
vided into 256 equal segments (see Figure 3). The 8 MSBs of
the digital input word select one of the 256 segments on the first
string. The taps at the top and bottom of the selected segment
are connected to the inputs of the two buffer amplifiers A1 and
A2. These amplifiers exhibit extremely high CMRR and low
bias current, and thus accurately preserve the voltages at the top
and bottom of the segment. The buffered voltages from the seg-
ment endpoints are applied across the second resistor string,
where the 8LSBs of the digital input word select one of the 256
taps. Output amplifier A3 buffers this voltage and delivers it to
the output.
Buffer amplifiers A1 and A2 leap-frog up the first string to pre-
serve monotonicity at the segment boundaries. For example,
when increasing the digital code from 00FFH to 0100H, (the first
segment boundary), A1 remains connected to the same tap on
the first resistor, while A2 jumps over it and is connected to the
tap which becomes the top of the next segment. This design
guarantees monotonicity even if the amplifiers have offset volt-
ages. In fact, amplifier offset only contributes to integral linear-
ity error.
CAUTION
It is generally considered good engineering practice to avoid
inserting integrated circuits into powered-up sockets. This
guideline is especially important with the AD569. An empty,
powered-up socket configures external buffer amplifiers in an
open-loop mode, forcing their outputs to be at the positive or
Figure 3. AD569 Block Diagram
negative rail. This condition may result in a large current surge
between the reference force and sense terminals. This current
surge may permanently damage the AD569.
ANALOG CIRCUIT DETAILS
Definitions
LINEARITY ERROR: Analog Devices defines linearity error as
the maximum deviation of the actual, adjusted DAC output
from the ideal output (a straight line drawn from 0 to FS–1LSB)
for any bit combination. The AD569’s linearity is primarily lim-
ited by resistor uniformity in the first divider (upper byte of
16-bit input). The plot in Figure 4 shows the AD569’s typical
linearity error across the entire output range to be within
± 0.01% of full scale. At 25°C the maximum linearity error for
the AD569JN, AD and SD grades is specified to be ± 0.04%,
and ± 0.024% for the KN and BD versions.
Figure 4. Typical Linearity
MONOTONICITY: A DAC is monotonic if the output either
increases or remains constant for increasing digital inputs. All
versions of the AD569 are monotonic over their full operating
temperature range.
DIFFERENTIAL NONLINEARITY: DNL is the measure of
the change in the analog output, normalized to full scale, associ-
ated: with a 1 LSB change in the digital input code. Monotonic
behavior requires that the differential linearity error be less than
1 LSB over the temperature range of interest. For example, for a
± 5 V output range, a change of 1 LSB in digital input code
should result in a 152 µV change in the analog output (1 LSB =
10 V/65,536). If the change is actually 38 µV, however, the dif-
ferential linearity error would be –114 µV, or –3/4 LSB. By leap-
frogging the buffer amplifier taps on the first divider, a typical
AD569 keeps DNL within ± 38 µV (± 1/4 LSB) around each of
the 256 segment boundaries defined by the upper byte of the in-
put word (see Figure 5). Within the second divider, DNL also
typically remains less than ± 38 µV as shown in Figure 6. Since
the second divider is independent of absolute voltage, DNL is
the same within the rest of the 256 segments.
OFFSET ERROR: The difference between the actual analog
output and the ideal output (–VREF), with the inputs loaded with
all zeros is called the offset error. For the AD569, Unipolar Off-
set is specified with 0 V applied to –VREF and Bipolar Offset is
specified with –5 V applied to –VREF. Either offset is trimmed by
adjusting the voltage applied to the –VREF terminals.
BIPOLAR ZERO ERROR: The deviation of the analog output
from the ideal half-scale output of 0.0000 V when the inputs are
loaded with 8000H is called the Bipolar Zero Error. For the
AD569, it is specified with ± 5 V applied to the reference
terminals.
REV. A
–5–
5 Page 
AD569
a. Simple Interface
b. Fast Interface
Figure 20. 8-Bit Microprocessor Interface
8-Bit Microprocessor Interfaces
Since 8-bit microprocessors require two write cycles to provide
the AD569’s 16-bit input, the DAC register must be utilized. It
is most often loaded as the second byte enters the first rank of
latches. This synchronous load method, shown in Figure 20, re-
quires LDAC to be tied to either LBE or HBE, depending upon
the byte loading sequence. In either case, the propagation delay
through the first rank gives rise to longer timing requirements as
shown in Figure 2. If the DAC register (LDAC) is controlled
separately using a third write cycle, the minimum write pulse on
LDAC is 70 ns, as shown in Figure 1.
Two basic methods exist for interfacing the AD569 to an 8-bit
microprocessor’s address and control buses. In either case, at
least one address line is needed to differentiate between the up-
per and lower bytes of the first rank (HBE and LBE). The sim-
plest method involves applying the two addresses directly to
HBE and LBE and strobing the data using CS as shown in Fig-
ure 20a. However, the minimum pulse width on CS is 70 ns
with a minimum data setup time of 60 ns. If operation with a
shorter pulse width is required, the base address should be ap-
plied to CS with an address line gated with the strobe signal to
supply the HBE and LBE inputs (see Figure 20b). However,
since the write pulse sees a propagation delay, the data still must
remain valid at least 20 ns after the rising edge of the delayed
write pulse.
OUTPUT SETTLING
The AD569’s output buffer amplifier typically settles to within
± 0.001% FS of its final value in 3 µs for a 10 V step. Figure 21
shows settling for negative and positive full-scale steps with no
load applied. Capable of sourcing or sinking 5 mA, the output
buffer can also drive loads of 1 kΩ and 1000 pF without loss of
stability. Typical settling to 0.001% under these worst-case con-
ditions is 4 µs, and is guaranteed to be a maximum of 6 µs. The
plots of Figure 21 were generated using the settling test proce-
dure developed specifically for the AD569.
Subranging 16-Bit ADC
The subranging ADC shown in Figure 22 completes a conver-
sion in less than 20 µs, including the sample-hold amplifier’s
sample time. The sample-hold amplifier is allocated 5 µs to
settle to 16 bits.
Before the first flash, the analog input signal is routed through
the AD630 at a gain of +1. The lower AD7820 quantizes the
signal to the 8-bit level within 1.4 µs, and the 8-bit result is
routed to the AD569 via a digital latch which holds the 8-bit
word for the AD569 and the output logic.
The AD569’s reference polarity is reversed so that a full-scale
output is –5 V and zero scale is 0 V, thereby subtracting an 8-bit
approximation from the original sampled signal. The residue
from the analog subtraction is then quantized by the second 8-
bit flash conversion to recover the 8 LSBs. Even though only the
AD569’s upper 8 MSBs are used, the AD569’s accuracy de-
fines the A/D converter’s overall accuracy. Any errors are di-
rectly reflected in the output.
REV. A
a. Turn-On Settling
b. Turn-Off Settling
Figure 21. Full-Scale Output Settling
–11–
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AD569.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD5601 | (AD5601 - AD5621) SPI Interface / SC70 Package / nanoDAC D/A | Analog Devices |
| AD5602 | 8-/10-/12-Bit nanoDACs | Analog Devices |
| AD561 | Low Cost 10-Bit Monolithic D/A Converter | Analog Devices |
| AD5611 | (AD5601 - AD5621) SPI Interface / SC70 Package / nanoDAC D/A | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |