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PDF AD781 Data sheet ( Hoja de datos )
| Número de pieza | AD781 | |
| Descripción | Complete 700 ns Sample-and-Hold Amplifier | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Acquisition Time to 0.01%: 700 ns Maximum
Low Power Dissipation: 95 mW
Low Droop Rate: 0.01 V/s
Fully Specified and Tested Hold Mode Distortion
Total Harmonic Distortion: –80 dB Maximum
Aperture Jitter: 75 ps Maximum
Internal Hold Capacitor
Self-Correcting Architecture
8-Pin Mini Cerdip and Plastic Package
MIL-STD-883 Compliant Versions Available
Complete 700 ns
Sample-and-Hold Amplifier
AD781*
FUNCTIONAL BLOCK DIAGRAM
VCC 1
IN 2
COMMON 3
NC 4
X1
AD781
8 OUT
7 S/H
6 NC
5 VEE
PRODUCT DESCRIPTION
The AD781 is a high speed monolithic sample-and-hold
amplifier (SHA). The AD781 guarantees a maximum
acquisition time of 700 ns to 0.01% over temperature. The
AD781 is specified and tested for hold mode total harmonic
distortion and hold mode signal-to-noise and distortion. The
AD781 is configured as a unity gain amplifier and uses a
self-correcting architecture that minimizes hold mode errors and
insures accuracy over temperature. The AD781 is self-contained
and requires no external components or adjustments.
The low power dissipation, 8-pin mini-DIP package and
completeness make the AD781 ideal for highly compact board
layouts. The AD781 will acquire a full-scale input in less than
700 ns and retain the held value with a droop rate of 0.01 µV/µs.
Excellent linearity and hold mode dc and dynamic performance
make the AD781 ideal for 12- and 14-bit high speed analog-
to-digital converters.
The AD781 is manufactured on Analog Devices’ BiMOS
process which merges high performance, low noise bipolar
circuitry with low power CMOS to provide an accurate, high
speed, low power SHA.
The AD781 is specified for three temperature ranges. The J
grade device is specified for operation from 0°C to +70°C, the A
grade from –40°C to +85°C and the S grade from –55°C to
+125°C. The J and A grades are available in 8-pin plastic DIP
packages. The S grade is available in an 8-pin cerdip package.
*Protected by U.S. Patent No. 4,962,325.
PRODUCT HIGHLIGHTS
1. Fast acquisition time (700 ns), low aperture jitter (75 ps) and
fully specified hold mode distortion make the AD781 an
ideal SHA for sampling systems.
2. Low droop (0.01 µV/µs) and internally compensated hold
mode error results in superior system accuracy.
3. Low power (95 mW typical), complete functionality and
small size make the AD781 an ideal choice for a variety of
high performance, low power applications.
4. The AD781 requires no external components or adjustments.
5. Excellent choice as a front-end SHA for high speed analog-
to-digital converters such as the AD671, AD7586, AD674B,
AD774B, AD7572 and AD7672.
6. Fully specified and tested hold mode distortion guarantees
the performance of the SHA in sampled data systems.
7. The AD781 is available in versions compliant with MIL-
STD-883. Refer to the Analog Devices Military Products
Databook or current AD781/883B data sheet for detailed
specifications.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
AD781
DEFINITIONS OF SPECIFICATIONS
Acquisition Time—The length of time that the SHA must
remain in the sample mode in order to acquire a full-scale input
step to a given level of accuracy.
Small Signal Bandwidth—The frequency at which the held
output amplitude is 3 dB below the input amplitude, under an
input condition of a 100 mV p-p sine wave.
Full Power Bandwidth—The frequency at which the held
output amplitude is 3 dB below the input amplitude, under an
input condition of a 10 V p-p sine wave.
Effective Aperture Delay—The difference between the switch
delay and the analog delay of the SHA channel. A negative
number indicates that the analog portion of the overall delay is
greater than the switch portion. This effective delay represents
the point in time, relative to the hold command, that the input
signal will be sampled.
Aperture Jitter—The variations in aperture delay for
successive samples. Aperture jitter puts an upper limit on the
maximum frequency that can be accurately sampled.
Hold Settling Time—The time required for the output to
settle to within a specified level of accuracy of its final held value
after the hold command has been given.
Droop Rate—The drift in output voltage while in the hold
mode.
Feedthrough—The attenuated version of a changing input
signal that appears at the output when the SHA is in the hold
mode.
Hold Mode Offset—The difference between the input signal
and the held output. This offset term applies only in the hold
mode and includes the error caused by charge injection and all
other internal offsets. It is specified for an input of 0 V.
Tracking Mode Offset—The difference between the input and
output signals when the SHA is in the track mode.
Nonlinearity--The deviation from a straight line on a plot of
input vs. (held) output as referenced to a straight line drawn
between endpoints, over an input range of –5 V and +5 V.
Gain Error—Deviation from a gain of +1 on the transfer
function of input vs. held output.
Power Supply Rejection Ratio—A measure of change in the
held output voltage for a specified change in the positive or
negative supply.
Sampled DC Uncertainty—The internal rms SHA noise that
is sampled onto the hold capacitor.
Hold Mode Noise—The rms noise at the output of the SHA
while in the hold mode, specified over a given bandwidth.
Total Output Noise—The total rms noise that is seen at the
output of the SHA while in the hold mode. It is the rms
summation of the sampled dc uncertainty and the hold mode
noise.
Output Drive Current—The maximum current the SHA can
source (or sink) while maintaining a change in hold mode offset
of less than 2.5 mV.
Signal-To-Noise and Distortion (S/N+D) Ratio—S/N+D is
the ratio of the rms value of the measured input signal to the
rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
S/N+D is expressed in decibels.
Total Harmonic Distortion (THD)—THD is the ratio of the
rms sum of the first six harmonic components to the rms value
of the measured input signal and is expressed as a percentage or
in decibels.
Intermodulation Distortion (IMD)—With inputs consisting
of sine waves at two frequencies, fa and fb, any device with
nonlinearities will create distortion products, of order (m+n), at
sum and difference frequency of mfa± nfb, where m, n = 0, 1, 2,
3.... Intermodulation terms are those for which m or n is not
equal to zero. For example, the second order terms are (fa+fb)
and (fa–fb), and the third order terms are (2fa+fb), (2fa–fb),
(fa+2fb) and (fa–2fb). The IMD products are expressed as the
decibel ratio of the rms sum of the measured input signals to the
rms sum of the distortion terms. The two signals are of equal
amplitude, and peak value of their sums is –0.5 dB from full
scale. The IMD products are normalized to a 0 dB input signal.
FUNCTIONAL DESCRIPTION
The AD781 is a complete sample-and hold amplifier that
provides high speed sampling to 12-bit accuracy in less than
700 ns.
The AD781 is completely self-contained, including an on-chip
hold capacitor, and requires no external components or
adjustments to perform the sampling function. Both input and
output are treated as a single-ended signal, referred to common.
The AD781 utilizes a proprietary circuit design which includes a
self-correcting architecture. This sample-and-hold circuit
corrects for internal errors after the hold command has been
given, by compensating for amplifier gain and offset errors, and
charge injection errors. Due to the nature of the design, the
SHA output in the sample mode is not intended to provide an
accurate representation of the input. However, in hold mode,
the internal circuitry is reconfigured to produce an accurately
held version of the input signal. Below is a block diagram of the
AD781.
VCC 1
IN 2
COMMON 3
X1
8 OUT
7 S/H
6 NC
NC 4
AD781 5 VEE
Functional Block Diagram
REV. A
–5–
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet AD781.PDF ] | |
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