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PDF AD7537 Data sheet ( Hoja de datos )
| Número de pieza | AD7537 | |
| Descripción | LC2MOS (8+4) Loading Dual 12-Bit DAC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Two 12-Bit DACs in One Package
DAC Ladder Resistance Matching: 0.5%
Space Saving Skinny DIP and Surface Mount Packages
4-Quadrant Multiplication
Low Gain Error (1 LSB max Over Temperature)
Byte Loading Structure
Fast Interface Timing
APPLICATIONS
Automatic Test Equipment
Programmable Filters
Audio Applications
Synchro Applications
Process Control
LC2MOS
(8+4) Loading Dual 12-Bit DAC
AD7537
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The AD7537 contains two 12-bit current output DACs on one
monolithic chip. A separate reference input is provided for each
DAC. The dual DAC saves valuable board space, and the
monolithic construction ensures excellent thermal tracking.
Both DACs are guaranteed 12-bit monotonic over the full tem-
perature range.
The AD7537 has a 2-byte (8 LSBs, 4 MSBs) loading structure.
It is designed for right-justified data format. The control signals
for register loading are A0, A1, CS, WR and UPD. Data is
loaded to the input registers when CS and WR are low. To
transfer this data to the DAC registers, UPD must be taken low
with WR.
Added features on the AD7537 include an asynchronous CLR
line which is very useful in calibration routines. When this is
taken low, all registers are cleared. The double buffering of the
data inputs allows simultaneous update of both DACs. Also,
each DAC has a separate AGND line. This increases the device
versatility; for instance one DAC may be operated with
AGND biased while the other is connected in the standard
configuration.
The AD7537 is manufactured using the Linear Compatible
CMOS (LC2MOS) process. It is speed compatible with most
microprocessors and accepts TTL, 74HC and 5 V CMOS logic
level inputs.
PRODUCT HIGHLIGHTS
1. DAC to DAC Matching:
Since both DACs are fabricated on the same chip, precise
matching and tracking is inherent. Many applications which
are not practical using two discrete DACs are now possible.
Typical matching: 0.5%.
2. Small Package Size:
The AD7537 is packaged in small 24-pin 0.3" DIPs and in
28-terminal surface mount packages.
3. Wide Power Supply Tolerance:
The device operates on a +12 V to +15 V VDD, with ± 10%
tolerance on this nominal figure. All specifications are
guaranteed over this range.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
Applications–AD7537
UNIPOLAR BINARY OPERATION
(2-QUADRANT MULTIPLICATION)
Figure 4 shows the circuit diagram for unipolar binary opera-
tion. With an ac input, the circuit performs 2-quadrant multipli-
cation. The code table for Figure 4 is given in Table II.
Operational amplifiers A1 and A2 can be in a single package
(AD644, AD712) or separate packages (AD544, AD711,
AD OP27). Capacitors C1 and C2 provide phase compensation
to help prevent overshoot and ringing when high-speed op amps
are used.
For zero offset adjustment, the appropriate DAC register is
loaded with all 0s and amplifier offset adjusted so that VOUTA or
VOUTB is 0 V. Full-scale trimming is accomplished by loading
the DAC register with all 1s and adjusting R1 (R3) so that
VOUTA (VOUTB) = –VIN (4095/4096). For high temperature op-
eration, resistors and potentiometers should have a low Tem-
perature Coefficient. In many applications, because of the
excellent Gain T.C. and Gain Error specifications of the
AD7537, Gain Error trimming is not necessary. In fixed refer-
ence applications, full scale can also be adjusted by omitting R1,
R2, R3, R4 and trimming the reference voltage magnitude.
BIPOLAR OPERATION
(4-QUADRANT MULTIPLICATION)
The recommended circuit diagram for bipolar operation is
shown in Figure 5. Offset binary coding is used.
With the appropriate DAC register loaded to 1000 0000 0000,
adjust R1 (R3) so that VOUTA (VOUTB) = 0 V. Alternatively, R1,
R2 (R3, R4) may be omitted and the ratios of R6, R7 (R9, 10)
varied for VOUTA (VOUTB) = 0 V. Full-scale trimming can be ac-
complished by adjusting the amplitude of VIN or by varying the
value of R5 (R8).
If R1, R2 (R3, R4) are not used, then resistors R5, R6, R7 (R8,
R9, R10) should be ratio matched to 0.01% to ensure gain error
performance to the data sheet specification. When operating
over a wide temperature range, it is important that the resistors
be of the same type so that their temperature coefficients match.
The code table for Figure 5 is given in Table III.
Figure 4. AD7537 Unipolar Binary Operation
Table II. Unipolar Binary Code Table for
Circuit of Figure 4
Binary Number in
DAC Register
MSB LSB
Analog Output,
VOUTA or VOUTB
1111 1111 1111
1000 0000 0000
0000 0000 0001
0000 0000 0000
REV. 0
−V
IN
4095
4096
−V IN
2048
4096
=
−
1
2
V
IN
−V
IN
1
4096
0V
Figure 5. Bipolar Operation (Offset Binary Coding)
Table III. Bipolar Code Table for Offset Binary
Circuit of Figure 5
Binary Number in
DAC Register
MSB
LSB
Analog Output,
VOUTA or VOUTB
1111 1111 1111
1000 0000 0001
1000 0000 0000
0111 1111 1111
0000 0000 0000
+V
IN
2047
2048
+V
IN
1
2048
0V
−V
IN
1
2048
−V
IN
2048
2048
=
−V
IN
–5–
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet AD7537.PDF ] | |
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