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PDF AD9754 Data sheet ( Hoja de datos )
| Número de pieza | AD9754 | |
| Descripción | 14-Bit/ 125 MSPS High Performance TxDAC D/A Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
14-Bit, 125 MSPS High Performance
TxDAC® D/A Converter
AD9754*
FEATURES
High Performance Member of Pin-Compatible
TxDAC Product Family
125 MSPS Update Rate
14-Bit Resolution
Excellent Spurious Free Dynamic Range Performance
SFDR to Nyquist @ 5 MHz Output: 83 dBc
Differential Current Outputs: 2 mA to 20 mA
Power Dissipation: 185 mW @ 5 V
Power-Down Mode: 20 mW @ 5 V
On-Chip 1.20 V Reference
CMOS-Compatible +2.7 V to +5.5 V Digital Interface
Package: 28-Lead SOIC, TSSOP Packages
Edge-Triggered Latches
APPLICATIONS
Wideband Communication Transmit Channel:
Direct IF
Basestations
Wireless Local Loop
Digital Radio Link
Direct Digital Synthesis (DDS)
Instrumentation
PRODUCT DESCRIPTION
The AD9754 is a 14-bit resolution, wideband, second genera-
tion member of the TxDAC series of high performance, low
power CMOS digital-to-analog-converters (DACs). The
TxDAC family, which consists of pin compatible 8-, 10-, 12-
and 14-bit DACs, is specifically optimized for the transmit
signal path of communication systems. All of the devices share
the same interface options, small outline package and pinout,
providing an upward or downward component selection path
based on performance, resolution and cost. The AD9754 offers
exceptional ac and dc performance while supporting update
rates up to 125 MSPS.
The AD9754’s flexible single-supply operating range of +4.5 V to
+5.5 V and low power dissipation are well suited for portable and
low power applications. Its power dissipation can be further reduc-
ed to a mere 65 mW with a slight degradation in performance by
lowering the full-scale current output. Also, a power-down mode
reduces the standby power dissipation to approximately 20 mW.
The AD9754 is manufactured on an advanced CMOS process.
A segmented current source architecture is combined with a
proprietary switching technique to reduce spurious components
and enhance dynamic performance. Edge-triggered input latches
and a 1.2 V temperature compensated bandgap reference have
been integrated to provide a complete monolithic DAC solution.
The digital inputs support +2.7 V and +5 V CMOS logic families.
TxDAC is a registered trademark of Analog Devices, Inc.
*Protected by U.S. Patents Numbers 5450084, 5568145, 5689257, 5612697 and
5703519. Other patents pending.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
+5V
0.1F
RSET +5V
CLOCK
REFLO
+1.20V REF
REFIO
FS ADJ
150pF
AVDD ACOM
CURRENT
SOURCE
ARRAY
AD9754
ICOMP 0.1F
DVDD
DCOM
SEGMENTED
SWITCHES
LSB
SWITCHES
IOUTA
IOUTB
CLOCK
SLEEP
LATCHES
DIGITAL DATA INPUTS (DB13–DB0)
The AD9754 is a current-output DAC with a nominal full-scale
output current of 20 mA and > 100 kΩ output impedance.
Differential current outputs are provided to support single-
ended or differential applications. Matching between the two
current outputs ensures enhanced dynamic performance in a
differential output configuration. The current outputs may be
tied directly to an output resistor to provide two complemen-
tary, single-ended voltage outputs or fed directly into a trans-
former. The output voltage compliance range is 1.25 V.
The on-chip reference and control amplifier are configured for
maximum accuracy and flexibility. The AD9754 can be driven
by the on-chip reference or by a variety of external reference
voltages. The internal control amplifier, which provides a wide
(>10:1) adjustment span, allows the AD9754 full-scale current
to be adjusted over a 2 mA to 20 mA range while maintaining
excellent dynamic performance. Thus, the AD9754 may operate
at reduced power levels or be adjusted over a 20 dB range to
provide additional gain ranging capabilities.
The AD9754 is available in 28-lead SOIC and TSSOP packages.
It is specified for operation over the industrial temperature range.
PRODUCT HIGHLIGHTS
1. The AD9754 is a member of the wideband TxDAC high per-
formance product family that provides an upward or downward
component selection path based on resolution (8 to 14 bits),
performance and cost. The entire family of TxDACs is avail-
able in industry standard pinouts.
2. Manufactured on a CMOS process, the AD9754 uses a
proprietary switching technique that enhances dynamic per-
formance beyond that previously attainable by higher power/
cost bipolar or BiCMOS devices.
3. On-chip, edge-triggered input CMOS latches readily inter-
face to +2.7 V to +5 V CMOS logic families. The AD9754
can support update rates up to 125 MSPS.
4. A flexible single-supply operating range of +4.5 V to +5.5 V,
and a wide full-scale current adjustment span of 2 mA to
20 mA, allows the AD9754 to operate at reduced power levels.
5. The current output(s) of the AD9754 can be easily config-
ured for various single-ended or differential circuit topologies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
1 page  
PIN CONFIGURATION
(MSB) DB13 1
28 CLOCK
DB12 2
27 DVDD
DB11 3
26 DCOM
DB10 4
25 NC
DB9 5
24 AVDD
AD9754
DB8 6 TOP VIEW 23 ICOMP
DB7 7 (Not to Scale) 22 IOUTA
DB6 8
21 IOUTB
DB5 9
20 ACOM
DB4 10
19 NC
DB3 11
18 FS ADJ
DB2 12
17 REFIO
DB1 13
16 REFLO
(LSB) DB0 14
15 SLEEP
NC = NO CONNECT
AD9754
Pin No.
1
2–13
14
15
16
17
18
19, 25
20
21
22
23
24
26
27
28
PIN FUNCTION DESCRIPTIONS
Name
Description
DB13
Most Significant Data Bit (MSB).
DB12–DB1 Data Bits 1–12.
DB0 Least Significant Data Bit (LSB).
SLEEP
Power-Down Control Input. Active High. Contains active pull-down circuit; it may be left unterminated if
not used.
REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference.
REFIO
Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to
AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM).
Requires 0.1 µF capacitor to ACOM when internal reference activated.
FS ADJ Full-Scale Current Output Adjust.
NC No Connect.
ACOM Analog Common.
IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s.
IOUTA DAC Current Output. Full-scale current when all data bits are 1s.
ICOMP Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 µF capacitor.
AVDD
Analog Supply Voltage (+4.5 V to +5.5 V).
DCOM Digital Common.
DVDD
Digital Supply Voltage (+2.7 V to +5.5 V).
CLOCK Clock Input. Data latched on positive edge of clock.
REV. A
–5–
5 Page 
AD9754
input impedance of REFIO is approximately 1 MΩ, a simple,
low cost R-2R ladder DAC configured in the voltage mode
topology may be used to control the gain. This circuit is shown
in Figure 19 using the AD7524 and an external 1.2 V reference,
the AD1580.
The second method may be used in a dual-supply system in
which the common-mode voltage of REFIO is fixed, and IREF is
varied by an external voltage, VGC, applied to RSET via an ampli-
fier. An example of this method is shown in Figure 25 in which
the internal reference is used to set the common-mode voltage
of the control amplifier to 1.20 V. The external voltage, VGC, is
referenced to ACOM and should not exceed 1.2 V. The value of
RSET is such that IREFMAX and IREFMIN do not exceed 62.5 µA
and 625 µA, respectively. The associated equations in Figure 20
can be used to determine the value of RSET.
AVDD
REFLO 150pF
+1.2V REF
AVDD
REFIO
1F FS ADJ
RSET IREF AD9754
CURRENT
SOURCE
ARRAY
VGC
IREF = (1.2 – VGC)/RSET
WITH VGC VREFIO AND 62.5A IREF 625A
Figure 20. Dual-Supply Gain Control Circuit
ANALOG OUTPUTS
The AD9754 produces two complementary current outputs,
IOUTA and IOUTB, which may be configured for single-end
or differential operation. IOUTA and IOUTB can be converted
into complementary single-ended voltage outputs, VOUTA and
VOUTB, via a load resistor, RLOAD, as described in the DAC
Transfer Function section by Equations 5 through 8. The
differential voltage, VDIFF, existing between VOUTA and VOUTB
can also be converted to a single-ended voltage via a transformer
or differential amplifier configuration.
Figure 21 shows the equivalent analog output circuit of the
AD9754 consisting of a parallel combination of PMOS differen-
tial current switches associated with each segmented current
source. The output impedance of IOUTA and IOUTB is deter-
mined by the equivalent parallel combination of the PMOS
switches and is typically 100 kΩ in parallel with 5 pF. Due to
the nature of a PMOS device, the output impedance is also
slightly dependent on the output voltage (i.e., VOUTA and VOUTB)
and, to a lesser extent, the analog supply voltage, AVDD, and
full-scale current, IOUTFS. Although the output impedance’s signal
dependency can be a source of dc nonlinearity and ac linearity
(i.e., distortion), its effects can be limited if certain precautions
are noted.
AD9754
AVDD
IOUTA
RLOAD
IOUTB
RLOAD
Figure 21. Equivalent Analog Output Circuit
IOUTA and IOUTB also have a negative and positive voltage
compliance range. The negative output compliance range of
–1.0 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a break-
down of the output stage and affect the reliability of the AD9754.
The positive output compliance range is slightly dependent on
the full-scale output current, IOUTFS. It degrades slightly from its
nominal 1.25 V for an IOUTFS = 20 mA to 1.00 V for an IOUTFS =
2 mA. Operation beyond the positive compliance range will
induce clipping of the output signal which severely degrades
the AD9754’s linearity and distortion performance.
For applications requiring the optimum dc linearity, IOUTA
and/or IOUTB should be maintained at a virtual ground via an
I-V op amp configuration. Maintaining IOUTA and/or IOUTB
at a virtual ground keeps the output impedance of the AD9754
fixed, significantly reducing its effect on linearity. However,
it does not necessarily lead to the optimum distortion perfor-
mance due to limitations of the I-V op amp. Note that the
INL/DNL specifications for the AD9754 are measured in
this manner using IOUTA. In addition, these dc linearity
specifications remain virtually unaffected over the specified
power supply range of +4.5 V to +5.5 V.
Operating the AD9754 with reduced voltage output swings at
IOUTA and IOUTB in a differential or single-ended output
configuration reduces the signal dependency of its output
impedance thus enhancing distortion performance. Although
the voltage compliance range of IOUTA and IOUTB extends
from –1.0 V to +1.25 V, optimum distortion performance is
achieved when the maximum full-scale signal at IOUTA and
IOUTB does not exceed approximately 0.5 V. A properly se-
lected transformer with a grounded center-tap will allow the
AD9754 to provide the required power and voltage levels to
different loads while maintaining reduced voltage swings at
IOUTA and IOUTB. DC-coupled applications requiring a
differential or single-ended output configuration should size
RLOAD accordingly. Refer to Applying the AD9754 section for
examples of various output configurations.
REV. A
–11–
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet AD9754.PDF ] | |
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