PDF AKD4383 Data sheet ( Hoja de datos )

Número de pieza	AKD4383
Descripción	192kHz 24-Bit 2ch ∆ DAC with DSD input
Fabricantes	Asahi Kasei Microsystems
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No Preview Available ! ASAHI KASEI [AK4383] AK4383 192kHz 24-Bit 2ch ∆Σ DAC with DSD input GENERAL DESCRIPTION The AK4383 offers the perfect mix for cost and performance based audio systems. Using AKM's multi bit architecture for its modulator the AK4383 delivers a wide dynamic range while preserving linearity for improved THD+N performance. The AK4383 has full differential SCF outputs, removing the need for AC coupling capacitors and increasing performance for systems with excessive clock jitter. The AK4383 accepts 192kHz PCM data and 1-Bit DSD data, ideal for a wide range of applications including DVD- Audio and SACD. The AK4383 is offered in a space saving 20pin TSSOP package. FEATURES Sampling Rate Ranging from 8kHz to 192kHz 24-Bit 8 times FIR Digital Filter On chip SCF Digital de-emphasis for 32k, 44.1k and 48kHz sampling Soft mute Digital Attenuator (Linear 256 steps) PCM I/F format: 24-Bit MSB justified, 24/20/16-Bit LSB justified or I2S Master clock: 256fs, 384fs, 512fs or 768fs (PCM Normal Speed Mode) 128fs, 192fs, 256fs or 384fs (PCM Double Speed Mode) 128fs or 192fs (PCM Quad Speed Mode) 512fs or 768fs (DSD Mode) THD+N: -94dB Dynamic Range: 110dB DSD Data Input Mode High Tolerance to Clock Jitter Power supply: 4.75 to 5.25V Very Small Package: 20pin TSSOP (0.65mm pitch) AK4382 Pin Compatible MCLK CSN CCLK CDTI LRCK/DSDR BICK/DCLK SDTI/DSDL DCLK DSDL DSDR µP Interface De-emphasis Control PCM Data Interface DSD Data Interface 8X Interpolator 8X Interpolator Clock Divider S&H ∆Σ Modulator SCF S&H ∆Σ Modulator SCF VDD VSS DZFL DZFR AOUTL+ AOUTL- AOUTR+ AOUTR- MS0090-E-00 PDN DSDM -1- 2001/4 1 page ASAHI KASEI [AK4383] ANALOG CHARACTERISTICS (Ta=25°C; VDD=5.0V; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Input Data; Measurement frequency=20Hz ∼ 20kHz; RL ≥2kΩ; PCM Mode; unless otherwise specified) Parameter min typ max Resolution 24 Dynamic Characteristics (Note 3) THD+N fs=44.1kHz 0dBFS -94 -87 BW=20kHz -60dBFS -48 - fs=96kHz 0dBFS -92 -84 BW=40kHz -60dBFS -45 - fs=192kHz 0dBFS -92 - BW=40kHz -60dBFS -45 - Dynamic Range (-60dBFS with A-weighted) (Note 4) 102 110 S/N (A-weighted) (Note 5) 102 110 Interchannel Isolation (1kHz) 90 110 Interchannel Gain Mismatch 0.2 0.5 DC Accuracy Gain Drift 100 - Output Voltage (Note 6) ±2.3 ±2.5 ±2.7 Load Resistance (Note 7) 2 Power Supplies Power Supply Current (VDD) Normal Operation (PDN = “H”, fs≤96kHz) Normal Operation (PDN = “H”, fs=192kHz) Power-Down Mode (PDN = “L”) (Note 8) 20 34 25 42 10 100 Notes: 3. Measured by Audio Precision (System Two). Refer to the evaluation board manual. 4. 100dB at 16bit data. 5. S/N does not depend on input bit length. 6. Full-scale voltage (0dB). Output voltage scales with the voltage of VREF, AOUT (typ.@0dB)=(AOUT+)-(AOUT-)=±2.5Vpp × VREF/5. 7. For AC-load. 4kΩ for DC-load. 8. All digital inputs including clock pins (MCLK, BICK and LRCK) are held VDD or VSS. Units Bits dB dB dB dB dB dB dB dB dB dB ppm/°C Vpp kΩ mA mA µA MS0090-E-00 -5- 2001/4 5 Page ASAHI KASEI [AK4383] LRCK fs 88.2kHz 96.0kHz 128fs 11.2896MHz 12.2880MHz MCLK 192fs 256fs 16.9344MHz 22.5792MHz 18.4320MHz 24.5760MHz 384fs 33.8688MHz 36.8640MHz BICK 64fs 5.6448MHz 6.1440MHz Table 4. System Clock Example (Double Speed Mode @Manual Setting Mode) LRCK fs 176.4kHz 192.0kHz MCLK 128fs 192fs 22.5792MHz 33.8688MHz 24.5760MHz 36.8640MHz BICK 64fs 11.2896MHz 12.2880MHz Table 5. System Clock Example (Quad Speed Mode @Manual Setting Mode) MCLK 512fs 768fs 256fs 384fs 128fs 192fs Sampling Speed Normal Double Quad Table 6. Sampling Speed (Auto Setting Mode) LRCK fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz 128fs - - - - - 22.5792 24.5760 192fs - - - - - 33.8688 36.8640 MCLK (MHz) 256fs 384fs -- -- -- 22.5792 33.8688 24.5760 36.8640 -- -- 512fs 16.3840 22.5792 24.5760 - - - - 768fs 24.5760 33.8688 36.8640 - - - - Sampling Speed Normal Double Quad Table 7. System Clock Example (Auto Setting Mode) 2) DSD Mode The external clocks, which are required to operate the AK4383, are MCLK and DCLK. The master clock (MCLK) should be synchronized with DSD clock (DCLK) but the phase is not critical. The frequency of MCLK is set by DCKS bit. DCKS MCLK DCLK 0 512fs 64fs 1 768fs 64fs Table 8. System Clock (fs=44.1kHz) MS0090-E-00 - 11 - 2001/4 11 Page

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