PDF ADF7023 Data sheet ( Hoja de datos )

Número de pieza	ADF7023
Descripción	ISM Band FSK/GFSK/OOK/MSK/GMSK Transceiver IC
Fabricantes	Analog Devices
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Data Sheet High Performance, Low Power, ISM Band FSK/GFSK/OOK/MSK/GMSK Transceiver IC ADF7023 FEATURES Ultralow power, high performance transceiver Frequency bands 862 MHz to 928 MHz 431 MHz to 464 MHz Data rates supported 1 kbps to 300 kbps 2.2 V to 3.6 V power supply Single-ended and differential PAs Low IF receiver with programmable IF bandwidths 100 kHz, 150 kHz, 200 kHz, 300 kHz Receiver sensitivity (BER) −116 dBm at 1.0 kbps, 2FSK, GFSK −107.5 dBm at 38.4 kbps, 2FSK, GFSK −102.5 dBm at 150 kbps, GFSK, GMSK −100 dBm at 300 kbps, GFSK, GMSK −104 dBm at 19.2 kbps, OOK Very low power consumption 12.8 mA in PHY_RX mode (maximum front-end gain) 24.1 mA in PHY_TX mode (10 dBm output, single-ended PA) 0.75 µA in PHY_SLEEP mode (32 kHz RC oscillator active) 1.28 µA in PHY_SLEEP mode (32 kHz XTAL oscillator active) 0.33 µA in PHY_SLEEP mode (Deep Sleep Mode 1) RF output power of −20 dBm to +13.5 dBm (single-ended PA) RF output power of −20 dBm to +10 dBm (differential PA) Patented fast settling automatic frequency control (AFC) Digital received signal strength indication (RSSI) Integrated PLL loop filter and Tx/Rx switch Fast automatic VCO calibration Automatic synthesizer bandwidth optimization On-chip, low-power, custom 8-bit processor Radio control Packet management Smart wake mode Packet management support Highly flexible for a wide range of packet formats Insertion/detection of preamble/sync word/CRC/address Manchester and 8b/10b data encoding and decoding Data whitening Smart wake mode Current saving low power mode with autonomous receiver wake up, carrier sense, and packet reception Downloadable firmware modules Image rejection calibration, fully automated (patent pending) 128-bit AES encryption/decryption with hardware acceleration and key sizes of 128 bits, 192 bits, and 256 bits Reed Solomon error correction with hardware acceleration 240-byte packet buffer for TX/RX data Efficient SPI control interface with block read/write access Integrated battery alarm and temperature sensor Integrated RC and 32.768 kHz crystal oscillator On-chip, 8-bit ADC 5 mm × 5 mm, 32-pin, LFCSP package APPLICATIONS Smart metering IEEE 802.15.4g Wireless MBUS Home automation Process and building control Wireless sensor networks (WSNs) Wireless healthcare Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved. 1 page Data Sheet ADF7023 Peripheral Features..........................................................................83 Analog-to-Digital Converter .....................................................83 Temperature Sensor ....................................................................83 Test DAC ......................................................................................83 Transmit Test Modes ..................................................................83 Silicon Revision Readback .........................................................83 Applications Information ...............................................................84 Application Circuit .....................................................................84 REVISION HISTORY 7/12—Rev. B to Rev. C Changes to Features Section ............................................................1 Changed 1.8 V to 2.2 V, General Description Section .................4 Changed 1.8 V to 2.2 V, Table 1 Summary ....................................6 Changed 1.8 V to 2.2 V, Table 2.......................................................7 Changes to Table 3 ............................................................................9 Changes to Table 5 ..........................................................................14 Changes to VDD Parameter, Table 6...............................................15 Changes to Timing Specifications Section...................................16 Deleted t1 from Table 7, Figure 2, and Figure 3...........................16 Changes to Table 9 ..........................................................................18 Changes to Figure 5 to Figure 10 ..................................................20 Changes to Figure 11, Figure 12 Caption, Figure 13 and Figure 14 Caption............................................................................21 Changes to Figure 19 Caption to Figure 21 Caption..................22 Changes to Figure 26 Caption .......................................................23 Changes to Figure 34 Caption .......................................................24 Changes to Figure 61 Caption and Figure 64 Caption...............29 Changes to Figure 72 ......................................................................31 Changes to PHY_SLEEP Section ..................................................33 Changes to Initialization After Application of Power Section, Initialization After Issuing the CMD_HW_RESET Command Section, Initialization on Transitioning from PHY_SLEEP (After CS Is Brought Low) Section, and Initialization After a WUC Timeout Section...................................................................35 Changes to CMD_RAM_LOAD_DONE (0xC7) Section .........37 Deleted CMD_SYNC (0xA2) Section ..........................................37 Changes to State Transition and Command Timing Section....38 Changes to Table 11 and Table 12 .................................................39 Changes to Addressing Section .....................................................45 Changes to Example Address Check Section, Table 18, and CRC Section ..............................................................................................46 Changes to Figure 79 ......................................................................47 Changes to Figure 81 and Figure 82 .............................................50 Changes to Figure 83 and Figure 84 .............................................51 Changes to CMD_FINISHED Description, Table 24.................53 Changes to Command Access Section .........................................56 Changes to Figure 97 ......................................................................63 Changes to Table 29 ........................................................................68 Added Calibrating the RC Oscillator Section, Performing a Fine Calibration of the RC Oscillator Section, and Performing a Coarse Calibration of the RC Oscillator Section ........................69 Host Processor Interface ............................................................85 PA/LNA Matching ......................................................................85 Command Reference ......................................................................87 Register Maps ..................................................................................88 BBRAM Register Description ...................................................90 MCR Register Description.......................................................100 Outline Dimensions......................................................................109 Ordering Guide .........................................................................109 Added Figure 103; Renumbered Sequentially.............................70 Changes to Writing a Module to Program RAM Section..........71 Changes to Automatic PA Ramp Section Equation and Image Channel Rejection Section.............................................................75 Changes to Temperature Sensor Section and Table 43 ..............83 Changes to Figure 110 ....................................................................84 Changes to Figure 111 and Figure 112.........................................85 Changes to Support for External PA and LNA Control Section and Table 45 .....................................................................................86 Changes to CMD_SYNC Description Column, Table 46..........87 Changes to Table 48 ........................................................................88 Changes to Table 49 ........................................................................89 Changes to SYNTH_LUT_CONTROL_1 Description Column, Table 70.............................................................................................93 Changes to Table 78 ........................................................................96 Changes to Table 79 ........................................................................97 Changes to Table 84 and Table 86 .................................................98 Changes to Table 94 ........................................................................99 Added Table 95, Table 96, and Table 97; Renumbered Sequentially ....................................................................................100 Changes to Table 101 ....................................................................101 Added Table 124 and Table 125...................................................105 3/11—Rev. A to Rev. B Changes to RSSI Method 3, Formula ...........................................72 Changes to RSSI Method 4, Step 3................................................72 Changes to RSSI Method 4, Step 5 Formula and Formula Approximation ................................................................................73 Added Register 0x361 to Table 49.................................................85 Added Table 129, Renumbered Subsequent Tables ..................104 2/11—Rev. 0 to Rev. A Changes to Table 9, DGUARD Description ................................18 Changes to Sport Mode in Receive Section.................................47 Changes to Crystal Oscillator Section, Typical Crystal Load Capacitance Tuning Range Value, and to Table 31.....................70 Changes to RSSI Method 3 Section ..............................................72 Changes to RSSI Method 4 Section ..............................................73 Changes to Table 41, 9.6 kbps and 1 kbps Data Rate Setup Values .....................................................................................78 Changes to Table 108, ADC_PD_N Description......................100 8/10—Revision 0: Initial Version Rev. C \| Page 3 of 112 5 Page Data Sheet RECEIVER SPECIFICATIONS Table 3. Parameter 2FSK/GFSK/MSK/GMSK INPUT SENSITIVITY, BIT ERROR RATE (BER) 1.0 kbps Min 10 kbps 38.4 kbps 50 kbps 100 kbps 150 kbps 200 kbps 300 kbps 2FSK/GFSK/MSK/GMSK INPUT SENSITIVITY, PACKET ERROR RATE (PER) 1.0 kbps 9.6 kbps 38.4 kbps 50 kbps 100 kbps 150 kbps 200 kbps 300 kbps OOK INPUT SENSITIVITY, PACKET ERROR RATE (PER) 19.2 kbps (38.4 kcps, Manchester Encoded) 2.4 kbps (4.8 kcps, Manchester Encoded) LNA AND MIXER, INPUT IP3 Minimum LNA Gain Maximum LNA Gain LNA AND MIXER, INPUT IP2 Max LNA Gain, Max Mixer Gain Min LNA Gain, Min Mixer Gain Typ −116 −111 −107.5 −106.5 −105 −104 −103 −100.5 −115.5 −110.6 −106 −104.3 −102.6 −101 −99.1 −97.9 −104.7 −109.7 −11.5 −12.2 18.5 27 ADF7023 Max Unit Test Conditions At BER = 1E − 3, RF frequency = 433 MHz, 868 MHz, 915 MHz, LNA and PA matched separately1 dBm Frequency deviation = 4.8 kHz, IF filter bandwidth = 100 kHz dBm Frequency deviation = 9.6 kHz, IF filter bandwidth = 100 kHz dBm Frequency deviation = 20 kHz, IF filter bandwidth = 100 kHz dBm Frequency deviation = 12.5 kHz, IF filter bandwidth = 100 kHz dBm Frequency deviation = 25 kHz, IF filter bandwidth = 100 kHz dBm Frequency deviation = 37.5 kHz, IF filter bandwidth = 150 kHz dBm Frequency deviation = 50 kHz, IF filter bandwidth = 200 kHz dBm Frequency deviation = 75 kHz, IF filter bandwidth = 300 kHz At PER = 1%, RF frequency = 433 MHz, 868 MHz, 915 MHz, LNA and PA matched separately1, packet length = 128 bits, packet mode dBm Frequency deviation = 4.8 kHz, IF filter bandwidth = 100 kHz dBm Frequency deviation = 9.6 kHz, IF filter bandwidth = 100 kHz dBm Frequency deviation = 20 kHz, IF filter bandwidth = 100 kHz dBm Frequency deviation = 12.5 kHz, IF filter bandwidth = 100 kHz dBm Frequency deviation = 25 kHz, IF filter bandwidth = 100 kHz dBm Frequency deviation = 37.5 kHz, IF filter bandwidth = 150 kHz dBm Frequency deviation = 50 kHz, IF filter bandwidth = 200 kHz dBm Frequency deviation = 75 kHz, IF filter bandwidth = 300 kHz At PER = 1%, RF frequency = 433 MHz, 868 MHz, 915 MHz, LNA and PA matched separately1, packet length = 128 bits, packet mode, IF filter bandwidth = 100 kHz dBm dBm dBm dBm dBm dBm Receiver LO frequency (fLO) = 914.8 MHz, fSOURCE1 = fLO + 0.4 MHz, fSOURCE2 = fLO + 0.7 MHz Receiver LO frequency (fLO) = 920.8 MHz, fSOURCE1 = fLO + 1.1 MHz, fSOURCE2 = fLO + 1.3 MHz Rev. C \| Page 9 of 112 11 Page

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