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PDF AD7457 Data sheet ( Hoja de datos )
| Número de pieza | AD7457 | |
| Descripción | 100 kSPS 12-Bit ADC | |
| Fabricantes | Analog Devices | |
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Low Power, Pseudo Differential, 100 kSPS
12-Bit ADC in an 8-Lead SOT-23
AD7457
FEATURES
Specified for VDD of 2.7 V to 5.25 V
Low power:
0.9 mW max at 100 kSPS with VDD = 3 V
3 mW max at 100 kSPS with VDD = 5 V
Pseudo differential analog input
Wide input bandwidth:
70 dB SINAD at 30 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface—SPI®-/QSPI™-/
MICROWIRE™-/DSP-compatible
Automatic power-down mode
8-lead SOT-23 package
APPLICATIONS
Transducer interface
Battery-powered systems
Data acquisition systems
Portable instrumentation
GENERAL DESCRIPTION
The AD7457 is a 12-bit, low power, successive approximation
(SAR) analog-to-digital converter that features a pseudo
differential analog input. This part operates from a single 2.7 V
to 5.25 V power supply and features throughput rates of up to
100 kSPS.
The part contains a low noise, wide bandwidth, differential
track-and-hold (T/H) amplifier that can handle input frequen-
cies in excess of 1 MHz. The reference voltage for the AD7457 is
applied externally to the VREF pin and can range from 100 mV to
VDD, depending on what suits the application.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the device to interface
with microprocessors or DSPs. The SAR architecture of this
part ensures that there are no pipeline delays.
The AD7457 uses advanced design techniques to achieve very
low power dissipation.
FUNCTIONAL BLOCK DIAGRAM
VDD
VIN+
VIN–
VREF
12-BIT
T/H SUCCESSIVE
APPROXIMATION
ADC
AD7457
CONTROL LOGIC
SCLK
SDATA
CS
GND
Figure 1.
PRODUCT HIGHLIGHTS
1. Operation with 2.7 V to 5.25 V power supplies.
2. Low power consumption. With a 3 V supply, the AD7457
offers 0.9 mW maximum power consumption for a
100 kSPS throughput rate.
3. Pseudo differential analog input.
4. Flexible power/serial clock speed management. The
conversion rate is determined by the serial clock, allowing
the power to be reduced as the conversion time is reduced
through the serial clock speed increase. Automatic power-
down after conversion allows the average power consump-
tion to be reduced.
5. Variable voltage reference input.
6. No pipeline delays.
7. Accurate control of the sampling instant via the CS input
and once-off conversion control.
8. ENOB > 10 bits typically with 500 mV reference.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved.
1 page  
AD7457
Parameter
POWER REQUIREMENTS
VDD
IDD7, 8
During Conversion6
Normal Mode (Static)
Normal Mode (Operational)
Power-Down
Power Dissipation
Normal Mode (Operational)
Power-Down
Test Conditions/Comments
VDD = 4.75 V to 5.25 V
VDD = 2.7 V to 3.6 V
SCLK on or off
VDD = 4.75 V to 5.25 V
VDD= 2.7 V to 3.6 V
SCLK on or off
VDD = 5 V
VDD = 3 V
VDD = 5 V; SCLK on or off
VDD = 3 V; SCLK on or off
B Version1
2.7/5.25
1.5
1.2
0.5
0.7
0.33
1
3
0.9
5
3
Unit
V min/max
mA max
mA max
mA typ
mA max
mA max
µA max
mW max
mW max
µW max
µW max
1 Temperature range for B version: −40°C to +85°C.
2 See the Terminology section.
3 Analog inputs with slew rates exceeding 27 V/µs (full-scale input sine wave > 3.5 MHz) within the acquisition time may cause an incorrect result to be returned by the
converter.
4 A dc input is applied to VIN– to provide a pseudo ground for VIN+.
5 The AD7457 is functional with a reference input range of 100 mV to VDD.
6 Guaranteed by characterization.
7 See the Power Consumption section.
8 Measured with a full-scale dc input.
Rev. A | Page 4 of 20
5 Page 
AD7457
TERMINOLOGY
Signal to (Noise + Distortion) Ratio (SINAD)
The measured ratio of SINAD at the output of the ADC. The
signal is the rms amplitude of the fundamental. Noise is the
sum of all nonfundamental signals up to half the sampling
frequency (fS/2), excluding dc. The ratio is dependent on the
number of quantization levels in the digitization process; the
more levels, the smaller the quantization noise. The theoretical
SINAD ratio for an ideal N-bit converter with a sine wave input
is given by
Signal to(Noise + Distortion) = (6.02 N + 1.76) dB
Therefore, for a 12-bit converter, the SINAD is 74 dB.
Total Harmonic Distortion (THD)
The ratio of the rms sum of harmonics to the fundamental. For
the AD7457, it is defined as
THD (dB) = 20 log V22 + V32 + V42 + V52 + V62
V1
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second to the
sixth harmonics.
Peak Harmonic or Spurious Noise
The ratio of the rms value of the next largest component in the
ADC output spectrum (up to fS/2 and excluding dc) to the rms
value of the fundamental. Normally, the value of this specifica-
tion is determined by the largest harmonic in the spectrum, but,
for ADCs where the harmonics are buried in the noise floor, it is
a noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion prod-
ucts at sum and difference frequencies of mfa ± nfb, where m, n
= 0, 1, 2, 3, and so on. Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second order terms include (fa + fb) and (fa − fb), while the
third order terms include (2fa + fb), (2fa − fb), (fa + 2fb) and
(fa − 2fb).
The AD7457 is tested using the CCIF standard, where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second order terms are usually distanced in fre-
quency from the original sine waves, while the third order terms
are usually at a frequency close to the input frequencies. As a
result, the second and third order terms are specified separately.
The calculation of the intermodulation distortion is as per the
total harmonic distortion specification, where it is the ratio of
the rms sum of the individual distortion products to the rms
amplitude of the sum of the fundamentals expressed in dB.
Aperture Delay
The amount of time from the leading edge of the sampling
clock until the ADC actually takes the sample.
Aperture Jitter
The sample-to-sample variation in the effective point in time at
which the actual sample is taken.
Full-Power Bandwidth
The full-power bandwidth of an ADC is that input frequency
at which the amplitude of the reconstructed fundamental is
reduced by 0.1 dB or 3 dB for a full-scale input.
Integral Nonlinearity (INL)
The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function.
Differential Nonlinearity (DNL)
The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
The deviation of the first code transition (000...000 to 000...001)
from the ideal (that is, AGND + 1 LSB).
Gain Error
The deviation of the last code transition (111...110 to 111...111)
from the ideal (that is, VREF − 1 LSB), after the offset error has
been adjusted out.
Track-and-Hold Acquisition Time
The minimum time required for the track-and-hold amplifier to
remain in track mode for its output to reach and settle to within
0.5 LSB of the applied input signal.
Power Supply Rejection Ratio (PSRR)
The ratio of the power in the ADC output at full-scale
frequency, f, to the power of a 100 mV p-p sine wave applied to
the ADC VDD supply of frequency fs. The frequency of this
input varies from 1 kHz to 1 MHz.
PSRR(dB) = 10 log(Pf/Pfs)
Pf is the power at frequency f in the ADC output; Pfs is the
power at frequency fs in the ADC output.
Rev. A | Page 10 of 20
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet AD7457.PDF ] | |
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