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PDF AD7538 Data sheet ( Hoja de datos )
| Número de pieza | AD7538 | |
| Descripción | Microprocessor-Compatible 14-Bit DAC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD7538 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
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LC2MOS
Microprocessor-Compatible 14-Bit DAC
AD7538
FEATURES
All grades 14-bit monotonic over the full temperature range
Low cost, 14-bit upgrade for 12-bit systems
14-bit parallel load with double buffered inputs
Small 24-pin, 0.30” DIP and SOIC
Low output leakage (<20 nA) over the full temperature range
APPLICATIONS
Microprocessor-based control systems
Digital audio
Precision servo control
Control and measurement in high temperature environments
FUNCTIONAL BLOCK DIAGRAM
AD7538
VDD
23
2 RFB
VREF 1
14-BIT DAC
3 IOUT
4 AGND
DAC REGISTER
20 LDAC
INPUT
REGISTER
14
6 19
DB13 TO DB0
5
DGND
Figure 1.
21 CS
22 WR
24
VSS
GENERAL DESCRIPTION
The AD7538 is a 14-bit monolithic CMOS digital-to-analog
converter (DAC) that uses laser trimmed thin-film resistors to
achieve excellent linearity.
The DAC is loaded by a single 14-bit wide word using standard
chip select and memory write logic. Double buffering, which is
optional using LDAC, allows simultaneous updates in a system
containing multiple AD7538s.
A novel low leakage configuration enables the AD7538 to
exhibit excellent output leakage current characteristics over
the specified temperature range.
The AD7538 is manufactured using the linear-compatible
CMOS (LC2MOS) process. It is speed compatible with most
microprocessors and accepts TTL or CMOS logic level inputs.
PRODUCT HIGHLIGHTS
1. Guaranteed Monotonicity.
The AD7538 is guaranteed monotonic to 14-bits over the
full temperature range for all grades.
2. Low Cost.
The AD7538, with its 14-bit dynamic range, affords a low
cost solution for 12-bit system upgrades.
3. Small Package Size.
The AD7538 is packaged in a small 24-pin, 0.3" DIP and a
24-pin SOIC.
4. Low Output Leakage.
By tying VSS (Pin 24) to a negative voltage, it is possible to
achieve a low output leakage current at high temperatures.
5. Wide Power Supply Tolerance.
The device operates on a +12 V to +15 V VDD, with a ±5%
tolerance on this nominal figure. All specifications are
guaranteed over this range.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
1 page  
AD7538
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for design guidance only and are not subject to test. VDD = 11.4 V to 15.75 V, VREF = 10 V, VPIN3 = VPIN4 =
0 V, VSS = 0 V or −300 mV, output amplifier is AD711 except where noted.
Table 2.
Parameter
Output Current Settling Time
TA = 25°C
TA = TMIN, TMAX
1.5
Digital-to-Analog Glitch Impulse
Multiplying Feedthrough Error
Power Supply Rejection
ΔGain/ΔVDD
Output Capacitance
COUT (Pin 3)
COUT (Pin 3)
Output Noise Voltage Density
(10 Hz to 100 kHz)
20
3
±0.01
260
130
15
5
±0.02
260
130
Unit
μs max
nV-sec typ
mV p-p typ
Test Conditions/Comments
To 0.003% of full-scale range
IOUT load= 100 Ω, CEXT = 13 pF DAC register alternately loaded
with all 1s and all 0s; typical value of settling time is 0.8 μs
Measured with VREF = 0 V. IOUT load = 100 Ω, CEXT = 13 pF; DAC
register alternately loaded with all 1s and all 0s
VREF = ±10 V, 10 kHz sine wave DAC
Register loaded with all 0s
% per % max ΔVDD = ±5%
pF max
pF max
DAC register loaded with all 1s
DAC register loaded with all 0s
nV√Hz typ
Measured between RFB and IOUT
TIMING CHARACTERISTICS
VDD = 11.4 V to 15.75 V, VREF = 10 V, VPIN3 = VPIN4 = 0 V, VSS = 0 V or −300 mV. All specifications TMIN to TMAX unless otherwise noted. See
Figure 2 for a timing diagram.
Table 3.
Parameter1
t1
t2
t3
t4
t5
t6
Limit at
TA = +25°C
0
0
170
170
140
20
Limit at TA = 0°C to +70°C
TA = −25°C to +85°C
0
0
200
200
160
20
Limit at
TA = −55°C to +125°C
0
0
240
240
180
30
Unit
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
CS to WR setup time
CS to WR hold time
LDAC pulse width
Write pulse width
Data setup time
Data hold time
1 Temperature range as follows: J, K Versions: 0°C to +70°C
A, B Versions: −25°C to +85°C
S, T Versions: −55°C to +125°C
Rev. B | Page 4 of 16
5 Page 
AD7538
CIRCUIT INFORMATION
EQUIVALENT CIRCUIT ANALYSIS
Figure 5 shows an equivalent circuit for the analog section
of the AD7538 DAC. The current source ILEAKAGE is composed
of surface and junction leakages. The RO resistor denotes the
equivalent output resistance of the DAC, which varies with
input code. COUT is the capacitance due to the current steering
switches and varies from about 90 pF to 180 pF (typical values)
depending upon the digital input. g(VREF, N) is the Thevenin
equivalent voltage generator due to the reference input voltage,
VREF, and the transfer function of the DAC ladder, N.
R/4
RFB
RO IOUT
g (VREF, N)
ILEAKAGE
COUT
AGND
Figure 5. AD7538 Equivalent Analog Output Circuit
DIGITAL SECTION
The digital inputs are designed to be both TTL and 5 V CMOS
compatible. All logic inputs are static protected MOS gates with
typical input currents of less than 1 nA. To minimize power supply
currents, it is recommended that the digital input voltages be
driven as close as possible to 0 V and 5 V logic levels.
UNIPOLAR BINARY OPERATION (2-QUADRANT
MULTIPLICATION)
Figure 6 shows the circuit diagram for unipolar binary
operation. With an ac input, the circuit performs 2-quadrant
multiplication. The code table for Figure 6 is given in Table 6.
Capacitor C1 provides phase compensation and helps prevent
overshoot and ringing when high-speed op amps are used.
VIN
LDAC
CS
WR
R1 VDD
20Ω
R2
10Ω
1
VREF
20 LDAC
21 CS
22 WR
23
VDD
2
RFB
AD7538
IOUT 3
AGND 4
C1
33pF
A1
AD711
DB13 TO DB0 DGND VSS
6 19
5 24
DIGITAL
INPUT DATA GND
C2
4.7µF
+
R3
1kΩ
R4
47kΩ
ANALOG
GND
–15V
Figure 6. Unipolar Binary Operation
VO
Table 6. Unipolar Binary Code Table
Binary Number In
DAC Register
MSB LSB
11 1111 1111 1111
10 0000 0000 0000
00 0000 0000 0001
00 0000 0000 0000
Analog Output, VOUT
−VIN(16,383/16,384)
−VIN(8192/16,384) = −½VIN
−VIN(1/16,384)
0V
For zero offset adjustment, the DAC register is loaded with
all 0s and amplifier offset (VOS) adjusted so that VOUT is 0 V.
Adjusting VOUT to 0 V is not necessary in many applications,
but it is recommended that VOS be no greater than (25 × 10−6)
(VREF) to maintain specified DAC accuracy (see the Application
Hints section).
Full-scale trimming is accomplished by loading the DAC
register with all 1s and adjusting R1 so that VOUTA = −VIN
(16,383/16,384). For high temperature operation, resistors
and potentiometers should have a low temperature coefficient.
In many applications, because of the excellent gain TC and
gain error specifications of the AD7538, gain error trimming is
not necessary. In fixed reference applications, full scale can also
be adjusted by omitting R1 and R2 and trimming the reference
voltage magnitude.
Rev. B | Page 10 of 16
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet AD7538.PDF ] | |
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