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Número de pieza | DS2406 | |
Descripción | Dual Addressable Switch Plus 1Kb Memory | |
Fabricantes | Maxim Integrated | |
Logotipo | ||
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FEATURES
Open drain PIO pins are controlled and their
logic level can be determined over 1-Wire®
bus for closed-loop control
Replaces and is fully compatible with
DS2407 but no user-programmable power-on
settings and no Hidden Mode
PIO channel A sink capability of 50mA at
0.4V with soft turn-on; channel B 8mA at
0.4V
Maximum operating voltage of 13V at
PIO-A, 6.5V at PIO-B
1024 bits user-programmable OTP EPROM
User-programmable status memory to
control the device
Multiple DS2406’s can be identified on a
common 1-Wire bus and be turned on or off
independently of other devices on the bus
Unique, factory-lasered and tested 64-bit
registration number (8-bit family code +
48-bit serial number + 8-bit CRC tester)
assures error-free selection and absolute
identity because no two parts are alike
On-chip CRC16 generator allows detection
of data transfer errors
Built-in multidrop controller ensures
compatibility with other 1-Wire net products
Reduces control, address, data, programming
and power to a single data pin
Directly connects to a single port pin of a
microprocessor and communicates at up to
15.4 kbits/s
Supports Conditional Search with user-
selectable condition
Vcc bondout for optional external supply to
the device (TSOC package only)
1-Wire communication operates over a wide
voltage range of 2.8V to 6.0V from -40°C to
+85°C
Low cost TO-92 and 6-pin TSOC packages
DS2406
Dual Addressable Switch
Plus 1Kb Memory
PIN ASSIGNMENT
TO-92
6-PIN TSOC PACKAGE
DALLAS
DS2406
16
25
34
TOP VIEW
SIDE VIEW
123
See Mech. Drawings
Section
1 2 3 BOTTOM VIEW
PIN DESCRIPTION
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
TO-92
Ground
Data
PIO-A
---
---
---
TSOC
Ground
Data
PIO-A
Vcc
NC
PIO-B
ORDERING INFORMATION
DS2406+
TO-92 Package
DS2406+T&R TO-92 Package, Tape & Reel
DS2406P+
6-pin TSOC Package
DS2406P+T&R TSOC Package, Tape & Reel
+ Indicates lead-free compliance.
1 of 32
033109
1 page DS2406
MEMORY MAP
The DS2406 has two memory sections, called data memory and status memory. The data memory
consists of 1024 bits of one-time programmable EPROM organized as 4 pages of 32 bytes each. The
address range of the device’s status memory is 8 bytes. The first seven bytes of status memory (addresses
0 to 6) are implemented as EPROM. The eighth byte (address 7) consists of static RAM. The complete
memory map is shown in Figure 5. The 8-bit scratchpad is an additional register that acts as a buffer when
writing the memory. Data is first written to the scratchpad and then verified by reading a 16-bit CRC
from the DS2406 that confirms proper receipt of the data and address. This process ensures data integrity
when programming the memory. If the buffer contents are correct, the bus master should transmit a
programming pulse (EPROM) or a dummy byte FFh (RAM) to transfer the data from the scratchpad to
the addressed memory location. The details for reading and programming the DS2406 are given in the
Memory Function Commands section.
DS2406 MEMORY MAP Figure 5
8-Bit Scratchpad
1K-Bit
EPROM
Page #
0
1
2
3
Address Range
0000h to 001Fh
0020h to 003Fh
0040h to 005Fh
0060h to 007Fh
Description
32-Byte final storage Data Memory
32-Byte final storage Data Memory
32-Byte final storage Data Memory
32-Byte final storage Data Memory
8 Bytes
Status
Memory
Valid Device
Settings 00
(SRAM)
Factory Redirection Bitmap of
Test Byte
Bytes
Used Pages
Write-Protect
Bits Data
Memory
DS2406 STATUS MEMORY MAP Figure 6
ADDRESS
0 (EPROM)
1 (EPROM)
2 (EPROM)
3 (EPROM)
4 (EPROM)
5 (EPROM)
6 (EPROM)
7 (SRAM)
BIT 7
BM3
1
1
1
1
BIT 6
BM2
1
1
1
1
Supply PIO-B
Indication Channel
(read only) Flip-flop
BIT 5 BIT 4 BIT 3 BIT 2
BM1
BM0
WP3
WP2
1111
1111
1111
1111
EPROM Factory Test byte
Don’t care, always reads 00
PIO-A CSS4 CSS3 CSS2
Channel Channel Channel Source
Flip-flop Select Select Select
BIT 1
WP1
Redir. 0
Redir. 1
Redir 2
Redir 3
CSS1
Source
Select
BIT 0
WP0
Redir. 0
Redir. 1
Redir 2
Redir 3
CSS0
Polarity
5 of 32
5 Page Memory Function Flow Chart (continued) Figure 7
DS2406
From Figure 7
1st Part
0Fh N
Write Memory
?
Y
Bus Master TX
TA1(T7:T0), TA2 (T15:T8)
DS2406 sets Memory
Address = (T15:T0)
Bus Master TX
Data Byte (D7:D0)
Legend:
Decision made
by Bus Master
Decision made
by DS2406
To Figure 7
55h N 3rd Part
Write Status
?
Y
Bus Master TX
TA1(T7:T0), TA2 (T15:T8)
DS2406 sets Memory
Address = (T15:T0)
Bus Master TX
Data Byte (D7:D0)
Bus Master RX CRC16 of Command,
Address, Data (1st pass); CRC16 of
Address, Data (subsequent passes)
Bus Master RX CRC16 of Command,
Address, Data (1st pass); CRC16 of
Address, Data (subsequent passes)
CRC
Correct ?
Y
Bus Master TX
Program Pulse
N
DS2406 copies Scratch-
pad to Data EPROM
Bus Master RX Byte
from Data EPROM
S
R
Bus Master
TX FFh or
Program Pulse
DS2406 copies
Scratchpad to
Volatile Status
N CRC
Correct ?
Y
N
Address < 7
?
Y
Bus Master TX
Program Pulse
DS2406 copies Scratch-
pad to Status EPROM
EPROM
N
Byte Correct
?
Y
End of
Data Mem.
?
N
Y
DS2406 increments
Address Counter
Bus Master RX
Byte From
Volatile Status
Bus Master TX
Reset Pulse
Bus Master RX Byte
from Status EPROM
N EPROM
Byte Correct
?
Y
DS2406 increments
Address Counter
DS2406 loads new Address
into CRC Generator
DS2406 TX
Presence Pulse
DS2406 loads new Address
into CRC Generator
Vertical
Spare
11 of 32
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet DS2406.PDF ] |
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